| developer | b23acff | 2021-06-20 16:48:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MTK_PTP3_COMMON_H |
| 8 | #define MTK_PTP3_COMMON_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | |
| 13 | /************************************************ |
| 14 | * CPU info |
| 15 | ************************************************/ |
| 16 | #define NR_PTP3_CFG_CPU U(8) |
| 17 | #define PTP3_CFG_CPU_START_ID_L U(0) |
| 18 | #define PTP3_CFG_CPU_START_ID_B U(4) |
| 19 | #define PTP3_CFG_CPU_END_ID U(7) |
| 20 | |
| 21 | #define NR_PTP3_CFG1_DATA U(2) |
| 22 | #define PTP3_CFG1_MASK 0x3000 |
| 23 | |
| 24 | #define NR_PTP3_CFG2_DATA U(5) |
| 25 | |
| 26 | #define PTP3_CFG3_MASK1 0x1180 |
| 27 | #define PTP3_CFG3_MASK2 0x35C0 |
| 28 | #define PTP3_CFG3_MASK3 0x3DC0 |
| 29 | |
| 30 | /************************************************ |
| 31 | * register read/write |
| 32 | ************************************************/ |
| 33 | #define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) |
| 34 | #define ptp3_clrsetbits(addr, clear, set) \ |
| 35 | mmio_clrsetbits_32((uintptr_t)addr, clear, set) |
| 36 | |
| 37 | /************************************************ |
| 38 | * config enum |
| 39 | ************************************************/ |
| 40 | enum PTP3_CFG { |
| 41 | PTP3_CFG_ADDR, |
| 42 | PTP3_CFG_VALUE, |
| 43 | NR_PTP3_CFG, |
| 44 | }; |
| 45 | |
| 46 | /************************************ |
| 47 | * prototype |
| 48 | ************************************/ |
| 49 | extern void ptp3_core_init(unsigned int core); |
| 50 | extern void ptp3_core_unInit(unsigned int core); |
| 51 | |
| 52 | #endif /* MTK_PTP3_COMMON_H */ |