Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 1 | TC Total Compute Platform |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 2 | ========================== |
| 3 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 4 | Some of the features of TC platform referenced in TF-A include: |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 5 | |
| 6 | - A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_ |
| 7 | to abstract power and system management tasks away from application |
| 8 | processors. The RAM firmware for SCP is included in the TF-A FIP and is |
| 9 | loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access |
| 10 | to AP SRAM). |
| 11 | - GICv4 |
| 12 | - Trusted Board Boot |
| 13 | - SCMI |
| 14 | - MHUv2 |
| 15 | |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 16 | Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1 |
| 17 | (TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A |
| 18 | is the CPUs supported as below: |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 19 | |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 20 | - TC0 has support for Cortex A510, Cortex A710 and Cortex X2. |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 21 | - TC1 has support for Cortex A510, Cortex Makalu and Cortex X3. |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 22 | - TC2 has support for Hayes and Hunter Arm CPUs. |
| 23 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 24 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 25 | Boot Sequence |
| 26 | ------------- |
| 27 | |
| 28 | The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts |
| 29 | executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from |
| 30 | FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2 |
| 31 | is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own |
| 32 | RAM and starts executing it. The AP then continues executing the rest of TF-A |
| 33 | stages including BL31 runtime stage and hands off executing to |
| 34 | Non-secure world (u-boot). |
| 35 | |
| 36 | Build Procedure (TF-A only) |
| 37 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 38 | |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 39 | - Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to |
| 40 | point to the toolchain folder. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 41 | |
| 42 | - Build TF-A: |
| 43 | |
| 44 | .. code:: shell |
| 45 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 46 | make PLAT=tc BL33=<path_to_uboot.bin> \ |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 47 | SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1,2} all fip |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 48 | |
| 49 | Enable TBBR by adding the following options to the make command: |
| 50 | |
| 51 | .. code:: shell |
| 52 | |
| 53 | MBEDTLS_DIR=<path_to_mbedtls_directory> \ |
| 54 | TRUSTED_BOARD_BOOT=1 \ |
| 55 | GENERATE_COT=1 \ |
| 56 | ARM_ROTPK_LOCATION=devel_rsa \ |
| 57 | ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem |
| 58 | |
Rupinderjit Singh | 820b3b6 | 2022-04-04 17:28:41 +0100 | [diff] [blame] | 59 | -------------- |
| 60 | |
| 61 | *Copyright (c) 2020-2022, Arm Limited. All rights reserved.* |
| 62 | |
| 63 | .. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads |