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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Soby Mathew327548c2017-07-13 15:19:51 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#ifndef __GICV3_H__
8#define __GICV3_H__
9
Soby Mathew327548c2017-07-13 15:19:51 +010010#include "utils_def.h"
11
Achin Gupta92712a52015-09-03 14:18:02 +010012/*******************************************************************************
13 * GICv3 miscellaneous definitions
14 ******************************************************************************/
15/* Interrupt group definitions */
Soby Mathew5c5c36b2015-12-03 14:12:54 +000016#define INTR_GROUP1S 0
17#define INTR_GROUP0 1
18#define INTR_GROUP1NS 2
Achin Gupta92712a52015-09-03 14:18:02 +010019
20/* Interrupt IDs reported by the HPPIR and IAR registers */
21#define PENDING_G1S_INTID 1020
22#define PENDING_G1NS_INTID 1021
23
24/* Constant to categorize LPI interrupt */
25#define MIN_LPI_ID 8192
26
27/*******************************************************************************
28 * GICv3 specific Distributor interface register offsets and constants.
29 ******************************************************************************/
30#define GICD_STATUSR 0x10
31#define GICD_SETSPI_NSR 0x40
32#define GICD_CLRSPI_NSR 0x48
33#define GICD_SETSPI_SR 0x50
34#define GICD_CLRSPI_SR 0x50
35#define GICD_IGRPMODR 0xd00
Soby Mathewaaf71c82016-07-26 17:46:56 +010036/*
37 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
38 * n >= 32, making the effective offset as 0x6100.
39 */
40#define GICD_IROUTER 0x6000
Achin Gupta92712a52015-09-03 14:18:02 +010041#define GICD_PIDR2_GICV3 0xffe8
42
43#define IGRPMODR_SHIFT 5
44
45/* GICD_CTLR bit definitions */
46#define CTLR_ENABLE_G1NS_SHIFT 1
47#define CTLR_ENABLE_G1S_SHIFT 2
48#define CTLR_ARE_S_SHIFT 4
49#define CTLR_ARE_NS_SHIFT 5
50#define CTLR_DS_SHIFT 6
51#define CTLR_E1NWF_SHIFT 7
52#define GICD_CTLR_RWP_SHIFT 31
53
54#define CTLR_ENABLE_G1NS_MASK 0x1
55#define CTLR_ENABLE_G1S_MASK 0x1
56#define CTLR_ARE_S_MASK 0x1
57#define CTLR_ARE_NS_MASK 0x1
58#define CTLR_DS_MASK 0x1
59#define CTLR_E1NWF_MASK 0x1
60#define GICD_CTLR_RWP_MASK 0x1
61
62#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT)
63#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT)
64#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT)
65#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT)
66#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT)
67#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT)
68#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT)
69
70/* GICD_IROUTER shifts and masks */
Soby Mathew327548c2017-07-13 15:19:51 +010071#define IROUTER_SHIFT 0
Achin Gupta92712a52015-09-03 14:18:02 +010072#define IROUTER_IRM_SHIFT 31
73#define IROUTER_IRM_MASK 0x1
74
Soby Mathew327548c2017-07-13 15:19:51 +010075#define NUM_OF_DIST_REGS 30
76
Achin Gupta92712a52015-09-03 14:18:02 +010077/*******************************************************************************
78 * GICv3 Re-distributor interface registers & constants
79 ******************************************************************************/
80#define GICR_PCPUBASE_SHIFT 0x11
81#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */
82#define GICR_CTLR 0x0
83#define GICR_TYPER 0x08
84#define GICR_WAKER 0x14
Soby Mathew327548c2017-07-13 15:19:51 +010085#define GICR_PROPBASER 0x70
86#define GICR_PENDBASER 0x78
Achin Gupta92712a52015-09-03 14:18:02 +010087#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80)
88#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100)
89#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180)
Soby Mathew327548c2017-07-13 15:19:51 +010090#define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + 0x200)
91#define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + 0x280)
92#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300)
93#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380)
Achin Gupta92712a52015-09-03 14:18:02 +010094#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400)
95#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00)
96#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04)
97#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00)
Soby Mathew327548c2017-07-13 15:19:51 +010098#define GICR_NSACR (GICR_SGIBASE_OFFSET + 0xe00)
Achin Gupta92712a52015-09-03 14:18:02 +010099
100/* GICR_CTLR bit definitions */
Soby Mathew327548c2017-07-13 15:19:51 +0100101#define GICR_CTLR_UWP_SHIFT 31
102#define GICR_CTLR_UWP_MASK 0x1
103#define GICR_CTLR_UWP_BIT (1U << GICR_CTLR_UWP_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100104#define GICR_CTLR_RWP_SHIFT 3
105#define GICR_CTLR_RWP_MASK 0x1
Soby Mathew327548c2017-07-13 15:19:51 +0100106#define GICR_CTLR_RWP_BIT (1U << GICR_CTLR_RWP_SHIFT)
107#define GICR_CTLR_EN_LPIS_BIT (1U << 0)
Achin Gupta92712a52015-09-03 14:18:02 +0100108
109/* GICR_WAKER bit definitions */
110#define WAKER_CA_SHIFT 2
111#define WAKER_PS_SHIFT 1
112
113#define WAKER_CA_MASK 0x1
114#define WAKER_PS_MASK 0x1
115
116#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT)
117#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT)
118
119/* GICR_TYPER bit definitions */
120#define TYPER_AFF_VAL_SHIFT 32
121#define TYPER_PROC_NUM_SHIFT 8
122#define TYPER_LAST_SHIFT 4
123
124#define TYPER_AFF_VAL_MASK 0xffffffff
125#define TYPER_PROC_NUM_MASK 0xffff
126#define TYPER_LAST_MASK 0x1
127
128#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT)
129
Soby Mathew327548c2017-07-13 15:19:51 +0100130#define NUM_OF_REDIST_REGS 30
131
Achin Gupta92712a52015-09-03 14:18:02 +0100132/*******************************************************************************
133 * GICv3 CPU interface registers & constants
134 ******************************************************************************/
135/* ICC_SRE bit definitions*/
136#define ICC_SRE_EN_BIT (1 << 3)
137#define ICC_SRE_DIB_BIT (1 << 2)
138#define ICC_SRE_DFB_BIT (1 << 1)
139#define ICC_SRE_SRE_BIT (1 << 0)
140
141/* ICC_IGRPEN1_EL3 bit definitions */
142#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
143#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
144
145#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
146#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)
147
148/* ICC_IGRPEN0_EL1 bit definitions */
149#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
150#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)
151
152/* ICC_HPPIR0_EL1 bit definitions */
153#define HPPIR0_EL1_INTID_SHIFT 0
154#define HPPIR0_EL1_INTID_MASK 0xffffff
155
156/* ICC_HPPIR1_EL1 bit definitions */
157#define HPPIR1_EL1_INTID_SHIFT 0
158#define HPPIR1_EL1_INTID_MASK 0xffffff
159
160/* ICC_IAR0_EL1 bit definitions */
161#define IAR0_EL1_INTID_SHIFT 0
162#define IAR0_EL1_INTID_MASK 0xffffff
163
164/* ICC_IAR1_EL1 bit definitions */
165#define IAR1_EL1_INTID_SHIFT 0
166#define IAR1_EL1_INTID_MASK 0xffffff
167
Soby Mathewf6f1a322017-07-18 16:12:45 +0100168/*****************************************************************************
169 * GICv3 ITS registers and constants
170 *****************************************************************************/
171
172#define GITS_CTLR 0x0
173#define GITS_IIDR 0x4
174#define GITS_TYPER 0x8
175#define GITS_CBASER 0x80
176#define GITS_CWRITER 0x88
177#define GITS_CREADR 0x90
178#define GITS_BASER 0x100
179
180/* GITS_CTLR bit definitions */
181#define GITS_CTLR_ENABLED_BIT 1
182#define GITS_CTLR_QUIESCENT_SHIFT 31
183#define GITS_CTLR_QUIESCENT_BIT (1U << GITS_CTLR_QUIESCENT_SHIFT)
184
Achin Gupta92712a52015-09-03 14:18:02 +0100185#ifndef __ASSEMBLY__
186
Soby Mathew327548c2017-07-13 15:19:51 +0100187#include <gic_common.h>
Achin Gupta92712a52015-09-03 14:18:02 +0100188#include <stdint.h>
Soby Mathewa0fedc42016-06-16 14:52:04 +0100189#include <types.h>
Soby Mathew327548c2017-07-13 15:19:51 +0100190#include <utils_def.h>
Achin Gupta92712a52015-09-03 14:18:02 +0100191
192#define gicv3_is_intr_id_special_identifier(id) \
193 (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
194
195/*******************************************************************************
196 * Helper GICv3 macros for SEL1
197 ******************************************************************************/
198#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\
199 IAR1_EL1_INTID_MASK
200#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\
201 HPPIR1_EL1_INTID_MASK
202#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id)
203
204
205/*******************************************************************************
206 * Helper GICv3 macros for EL3
207 ******************************************************************************/
208#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\
209 IAR0_EL1_INTID_MASK
210#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id)
211
Soby Mathew327548c2017-07-13 15:19:51 +0100212/*
213 * This macro returns the total number of GICD registers corresponding to
214 * the name.
215 */
216#define GICD_NUM_REGS(reg_name) \
217 DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT))
218
219#define GICR_NUM_REGS(reg_name) \
220 DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT))
221
Achin Gupta92712a52015-09-03 14:18:02 +0100222/*******************************************************************************
223 * This structure describes some of the implementation defined attributes of the
224 * GICv3 IP. It is used by the platform port to specify these attributes in order
225 * to initialise the GICV3 driver. The attributes are described below.
226 *
227 * 1. The 'gicd_base' field contains the base address of the Distributor
228 * interface programmer's view.
229 *
230 * 2. The 'gicr_base' field contains the base address of the Re-distributor
231 * interface programmer's view.
232 *
233 * 3. The 'g0_interrupt_array' field is a ponter to an array in which each
234 * entry corresponds to an ID of a Group 0 interrupt.
235 *
236 * 4. The 'g0_interrupt_num' field contains the number of entries in the
237 * 'g0_interrupt_array'.
238 *
239 * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each
240 * entry corresponds to an ID of a Group 1 interrupt.
241 *
242 * 6. The 'g1s_interrupt_num' field contains the number of entries in the
243 * 'g1s_interrupt_array'.
244 *
245 * 7. The 'rdistif_num' field contains the number of Redistributor interfaces
246 * the GIC implements. This is equal to the number of CPUs or CPU interfaces
247 * instantiated in the GIC.
248 *
249 * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry
250 * for storing the base address of the Redistributor interface frame of each
251 * CPU in the system. The size of the array = 'rdistif_num'. The base
252 * addresses are detected during driver initialisation.
253 *
254 * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the
255 * driver will use to convert an MPIDR value to a linear core index. This
256 * index will be used for accessing the 'rdistif_base_addrs' array. This is
257 * an optional field. A GICv3 implementation maps each MPIDR to a linear core
258 * index as well. This mapping can be found by reading the "Affinity Value"
259 * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
260 * "Processor Numbers" are suitable to index into an array to access core
261 * specific information. If this not the case, the platform port must provide
262 * a hash function. Otherwise, the "Processor Number" field will be used to
263 * access the array elements.
264 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100265typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
Achin Gupta92712a52015-09-03 14:18:02 +0100266
267typedef struct gicv3_driver_data {
268 uintptr_t gicd_base;
269 uintptr_t gicr_base;
270 unsigned int g0_interrupt_num;
271 unsigned int g1s_interrupt_num;
272 const unsigned int *g0_interrupt_array;
273 const unsigned int *g1s_interrupt_array;
274 unsigned int rdistif_num;
275 uintptr_t *rdistif_base_addrs;
276 mpidr_hash_fn mpidr_to_core_pos;
277} gicv3_driver_data_t;
278
Soby Mathew327548c2017-07-13 15:19:51 +0100279typedef struct gicv3_redist_ctx {
280 /* 64 bits registers */
281 uint64_t gicr_propbaser;
282 uint64_t gicr_pendbaser;
283
284 /* 32 bits registers */
285 uint32_t gicr_ctlr;
286 uint32_t gicr_igroupr0;
287 uint32_t gicr_isenabler0;
288 uint32_t gicr_ispendr0;
289 uint32_t gicr_isactiver0;
290 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
291 uint32_t gicr_icfgr0;
292 uint32_t gicr_icfgr1;
293 uint32_t gicr_igrpmodr0;
294 uint32_t gicr_nsacr;
295} gicv3_redist_ctx_t;
296
297typedef struct gicv3_dist_ctx {
298 /* 64 bits registers */
299 uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM];
300
301 /* 32 bits registers */
302 uint32_t gicd_ctlr;
303 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
304 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
305 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
306 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
307 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
308 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
309 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
310 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
311} gicv3_dist_ctx_t;
312
Soby Mathewf6f1a322017-07-18 16:12:45 +0100313typedef struct gicv3_its_ctx {
314 /* 64 bits registers */
315 uint64_t gits_cbaser;
316 uint64_t gits_cwriter;
317 uint64_t gits_baser[8];
318
319 /* 32 bits registers */
320 uint32_t gits_ctlr;
321} gicv3_its_ctx_t;
322
Achin Gupta92712a52015-09-03 14:18:02 +0100323/*******************************************************************************
324 * GICv3 EL3 driver API
325 ******************************************************************************/
326void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
327void gicv3_distif_init(void);
328void gicv3_rdistif_init(unsigned int proc_num);
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000329void gicv3_rdistif_on(unsigned int proc_num);
330void gicv3_rdistif_off(unsigned int proc_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100331void gicv3_cpuif_enable(unsigned int proc_num);
332void gicv3_cpuif_disable(unsigned int proc_num);
333unsigned int gicv3_get_pending_interrupt_type(void);
334unsigned int gicv3_get_pending_interrupt_id(void);
335unsigned int gicv3_get_interrupt_type(unsigned int id,
336 unsigned int proc_num);
Soby Mathew327548c2017-07-13 15:19:51 +0100337void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
338void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
339/*
340 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
341 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
342 * implementation-defined sequence is needed at these steps, an empty function
343 * can be provided.
344 */
345void gicv3_distif_post_restore(unsigned int proc_num);
346void gicv3_distif_pre_save(unsigned int proc_num);
347void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
348void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100349void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
350void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
Achin Gupta92712a52015-09-03 14:18:02 +0100351
352#endif /* __ASSEMBLY__ */
353#endif /* __GICV3_H__ */