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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
Michal Simekd4ff2722023-04-20 08:01:03 +02003 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08006 */
7
8#include <assert.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08009#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <bl31/bl31.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053014#include <common/fdt_fixup.h>
15#include <common/fdt_wrappers.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053016#include <lib/mmio.h>
17#include <libfdt.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000018#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
Prasad Kummarib72494e2023-09-19 22:15:05 +053020#include <plat_console.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021
Amit Nagal71e1ffc2023-02-23 21:37:23 +053022#include <custom_svc.h>
Amit Nagalf7c85f82023-09-27 15:13:42 +053023#include <plat_fdt.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000024#include <plat_private.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053025#include <plat_startup.h>
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070026#include <zynqmp_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000027
Michal Simek53865b02021-05-27 09:42:37 +020028
Soren Brinkmann76fcae32016-03-06 20:16:27 -080029static entry_point_info_t bl32_image_ep_info;
30static entry_point_info_t bl33_image_ep_info;
31
32/*
33 * Return a pointer to the 'entry_point_info' structure of the next image for
34 * the security state specified. BL33 corresponds to the non-secure image type
35 * while BL32 corresponds to the secure image type. A NULL pointer is returned
36 * if the image does not exist.
37 */
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053038struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039{
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053040 entry_point_info_t *next_image_info;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080041
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053042 assert(sec_state_is_valid(type));
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070043 if (type == NON_SECURE) {
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053044 next_image_info = &bl33_image_ep_info;
45 } else {
46 next_image_info = &bl32_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070047 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080048
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053049 return next_image_info;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080050}
51
52/*
Alistair Francisb8d474f2017-11-30 16:21:21 -080053 * Set the build time defaults. We want to do this when doing a JTAG boot
54 * or if we can't find any other config data.
55 */
56static inline void bl31_set_default_config(void)
57{
58 bl32_image_ep_info.pc = BL32_BASE;
59 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
60 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
61 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
62 DISABLE_ALL_EXCEPTIONS);
63}
64
65/*
Soren Brinkmann76fcae32016-03-06 20:16:27 -080066 * Perform any BL31 specific platform actions. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010067 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
Soren Brinkmann76fcae32016-03-06 20:16:27 -080068 * are lost (potentially). This needs to be done before the MMU is initialized
69 * so that the memory layout can be used while creating page tables.
70 */
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010071void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
72 u_register_t arg2, u_register_t arg3)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080073{
Prasad Kummarie0783112023-04-26 11:02:07 +053074 uint64_t tfa_handoff_addr;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080075
Prasad Kummarib72494e2023-09-19 22:15:05 +053076 setup_console();
77
Soren Brinkmann76fcae32016-03-06 20:16:27 -080078 /* Initialize the platform config for future decision making */
79 zynqmp_config_setup();
80
Soren Brinkmann76fcae32016-03-06 20:16:27 -080081 /*
82 * Do initial security configuration to allow DRAM/device access. On
83 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
84 * other platforms might have more programmable security devices
85 * present.
86 */
87
Michal Simekef8f5592015-06-15 14:22:50 +020088 /* Populate common information for BL32 and BL33 */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080089 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080091 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080092 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
93
Prasad Kummarie0783112023-04-26 11:02:07 +053094 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070095
Michal Simekef8f5592015-06-15 14:22:50 +020096 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
Alistair Francisb8d474f2017-11-30 16:21:21 -080097 bl31_set_default_config();
Michal Simekef8f5592015-06-15 14:22:50 +020098 } else {
Prasad Kummari07795fa2023-06-08 21:36:38 +053099 /* use parameters from XBL */
100 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700101 &bl33_image_ep_info,
Prasad Kummarie0783112023-04-26 11:02:07 +0530102 tfa_handoff_addr);
Prasad Kummari07795fa2023-06-08 21:36:38 +0530103 if (ret != XBL_HANDOFF_SUCCESS) {
Siva Durga Prasad Paladugu8f499722018-05-17 15:17:46 +0530104 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700105 }
Michal Simekef8f5592015-06-15 14:22:50 +0200106 }
Venkatesh Yadav Abbarapu3a33f932022-05-04 14:27:56 +0530107 if (bl32_image_ep_info.pc != 0) {
Akshay Belsarede7a1cc2023-03-27 10:41:54 +0530108 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
Venkatesh Yadav Abbarapu621c1b22020-01-10 03:01:35 -0700109 }
Venkatesh Yadav Abbarapu3a33f932022-05-04 14:27:56 +0530110 if (bl33_image_ep_info.pc != 0) {
Akshay Belsarede7a1cc2023-03-27 10:41:54 +0530111 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
Venkatesh Yadav Abbarapu621c1b22020-01-10 03:01:35 -0700112 }
Amit Nagal71e1ffc2023-02-23 21:37:23 +0530113
114 custom_early_setup();
115
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800116}
117
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530118#if ZYNQMP_WDT_RESTART
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530119static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530120
121int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
122{
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530123 static uint32_t index;
124 uint32_t i;
125
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530126 /* Validate 'handler' and 'id' parameters */
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530127 if (!handler || index >= MAX_INTR_EL3) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530128 return -EINVAL;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700129 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530130
131 /* Check if a handler has already been registered */
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530132 for (i = 0; i < index; i++) {
133 if (id == type_el3_interrupt_table[i].id) {
134 return -EALREADY;
135 }
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700136 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530137
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530138 type_el3_interrupt_table[index].id = id;
139 type_el3_interrupt_table[index].handler = handler;
140
141 index++;
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530142
143 return 0;
144}
145
146static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
147 void *handle, void *cookie)
148{
149 uint32_t intr_id;
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530150 uint32_t i;
151 interrupt_type_handler_t handler = NULL;
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530152
153 intr_id = plat_ic_get_pending_interrupt_id();
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530154
155 for (i = 0; i < MAX_INTR_EL3; i++) {
156 if (intr_id == type_el3_interrupt_table[i].id) {
157 handler = type_el3_interrupt_table[i].handler;
158 }
159 }
160
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700161 if (handler != NULL) {
Prasad Kummarieeef80d2023-05-11 14:58:13 +0530162 return handler(intr_id, flags, handle, cookie);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700163 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530164
165 return 0;
166}
167#endif
168
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800169void bl31_platform_setup(void)
170{
Michal Simekeb2c0c02023-02-13 14:35:21 +0100171 prepare_dtb();
Michal Simek53865b02021-05-27 09:42:37 +0200172
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800173 /* Initialize the gic cpu and distributor interfaces */
174 plat_arm_gic_driver_init();
175 plat_arm_gic_init();
176}
177
178void bl31_plat_runtime_setup(void)
179{
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530180#if ZYNQMP_WDT_RESTART
181 uint64_t flags = 0;
182 uint64_t rc;
183
184 set_interrupt_rm_flag(flags, NON_SECURE);
185 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
186 rdo_el3_interrupt_handler, flags);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700187 if (rc) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530188 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700189 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530190#endif
Akshay Belsaree8af4da2023-04-06 11:09:20 +0530191
192 custom_runtime_setup();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800193}
194
195/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100196 * Perform the very early platform specific architectural setup here.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800197 */
198void bl31_plat_arch_setup(void)
199{
200 plat_arm_interconnect_init();
201 plat_arm_interconnect_enter_coherency();
202
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100203 const mmap_region_t bl_regions[] = {
Akshay Belsareec0afc82023-02-27 12:04:26 +0530204#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
Michal Simek53865b02021-05-27 09:42:37 +0200205 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
206 MT_MEMORY | MT_RW | MT_NS),
207#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100208 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
209 MT_MEMORY | MT_RW | MT_SECURE),
210 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
211 MT_CODE | MT_SECURE),
212 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
213 MT_RO_DATA | MT_SECURE),
214 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
215 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
216 MT_DEVICE | MT_RW | MT_SECURE),
217 {0}
218 };
219
Amit Nagal71e1ffc2023-02-23 21:37:23 +0530220 custom_mmap_add();
221
Roberto Vargas344ff022018-10-19 16:44:18 +0100222 setup_page_tables(bl_regions, plat_arm_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100223 enable_mmu_el3(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800224}