blob: bd601e4b39be2c258f0f38f07c13dc9c5b305382 [file] [log] [blame]
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05301/*
Harvey Hsiehb9b374f2016-11-15 22:04:51 +08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05305 */
6
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05307#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <arch_helpers.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <lib/mmio.h>
14#include <lib/utils.h>
15#include <lib/xlat_tables/xlat_tables_v2.h>
16
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053017#include <mce.h>
18#include <memctrl.h>
19#include <memctrl_v2.h>
Varun Wadekar87e44ff2016-03-03 13:22:39 -080020#include <smmu.h>
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053021#include <tegra_def.h>
Varun Wadekare81177d2016-07-18 17:43:41 -070022#include <tegra_platform.h>
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053023
24/* Video Memory base and size (live values) */
25static uint64_t video_mem_base;
Varun Wadekar7058aee2016-04-25 09:01:46 -070026static uint64_t video_mem_size_mb;
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053027
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053028/*
Varun Wadekar87e44ff2016-03-03 13:22:39 -080029 * Init Memory controller during boot.
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053030 */
31void tegra_memctrl_setup(void)
32{
33 uint32_t val;
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053034 const uint32_t *mc_streamid_override_regs;
35 uint32_t num_streamid_override_regs;
36 const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
37 uint32_t num_streamid_sec_cfgs;
Anthony Zhou0844b972017-06-28 16:35:54 +080038 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
Varun Wadekarad45ef72017-04-03 13:44:57 -070039 uint32_t i;
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053040
41 INFO("Tegra Memory Controller (v2)\n");
42
Varun Wadekar6cb25f92016-12-19 11:17:54 -080043#if ENABLE_SMMU_DEVICE
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053044 /* Program the SMMU pagesize */
Varun Wadekar87e44ff2016-03-03 13:22:39 -080045 tegra_smmu_init();
Varun Wadekar6cb25f92016-12-19 11:17:54 -080046#endif
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053047 /* Get the settings from the platform */
Anthony Zhou4408e882017-07-07 14:29:51 +080048 assert(plat_mc_settings != NULL);
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053049 mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
50 num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
51 mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
52 num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053053
54 /* Program all the Stream ID overrides */
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053055 for (i = 0; i < num_streamid_override_regs; i++)
56 tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053057 MC_STREAM_ID_MAX);
58
59 /* Program the security config settings for all Stream IDs */
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053060 for (i = 0; i < num_streamid_sec_cfgs; i++) {
61 val = mc_streamid_sec_cfgs[i].override_enable << 16 |
62 mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
63 mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
64 tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053065 }
66
67 /*
68 * All requests at boot time, and certain requests during
69 * normal run time, are physically addressed and must bypass
70 * the SMMU. The client hub logic implements a hardware bypass
71 * path around the Translation Buffer Units (TBU). During
72 * boot-time, the SMMU_BYPASS_CTRL register (which defaults to
73 * TBU_BYPASS mode) will be used to steer all requests around
74 * the uninitialized TBUs. During normal operation, this register
75 * is locked into TBU_BYPASS_SID config, which routes requests
76 * with special StreamID 0x7f on the bypass path and all others
77 * through the selected TBU. This is done to disable SMMU Bypass
78 * mode, as it could be used to circumvent SMMU security checks.
79 */
80 tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053081 MC_SMMU_BYPASS_CONFIG_SETTINGS);
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053082
Varun Wadekarc9ac3e42016-02-17 15:07:49 -080083 /*
Varun Wadekara0f26972016-03-11 17:18:51 -080084 * Re-configure MSS to allow ROC to deal with ordering of the
85 * Memory Controller traffic. This is needed as the Memory Controller
86 * boots with MSS having all control, but ROC provides a performance
87 * boost as compared to MSS.
88 */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053089 if (plat_mc_settings->reconfig_mss_clients != NULL) {
90 plat_mc_settings->reconfig_mss_clients();
91 }
Varun Wadekara0f26972016-03-11 17:18:51 -080092
Varun Wadekarad45ef72017-04-03 13:44:57 -070093 /* Program overrides for MC transactions */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053094 if (plat_mc_settings->set_txn_overrides != NULL) {
95 plat_mc_settings->set_txn_overrides();
96 }
Varun Wadekar87e44ff2016-03-03 13:22:39 -080097}
Varun Wadekarc9ac3e42016-02-17 15:07:49 -080098
Varun Wadekar87e44ff2016-03-03 13:22:39 -080099/*
100 * Restore Memory Controller settings after "System Suspend"
101 */
102void tegra_memctrl_restore_settings(void)
103{
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530104 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
105
106 assert(plat_mc_settings != NULL);
107
Varun Wadekara0f26972016-03-11 17:18:51 -0800108 /*
109 * Re-configure MSS to allow ROC to deal with ordering of the
110 * Memory Controller traffic. This is needed as the Memory Controller
111 * resets during System Suspend with MSS having all control, but ROC
112 * provides a performance boost as compared to MSS.
113 */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530114 if (plat_mc_settings->reconfig_mss_clients != NULL) {
115 plat_mc_settings->reconfig_mss_clients();
116 }
Varun Wadekara0f26972016-03-11 17:18:51 -0800117
Varun Wadekarad45ef72017-04-03 13:44:57 -0700118 /* Program overrides for MC transactions */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530119 if (plat_mc_settings->set_txn_overrides != NULL) {
120 plat_mc_settings->set_txn_overrides();
121 }
Varun Wadekarad45ef72017-04-03 13:44:57 -0700122
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530123 /* video memory carveout region */
Anthony Zhou0e07e452017-07-26 17:16:54 +0800124 if (video_mem_base != 0ULL) {
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530125 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
126 (uint32_t)video_mem_base);
127 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
128 (uint32_t)(video_mem_base >> 32));
Varun Wadekar7058aee2016-04-25 09:01:46 -0700129 tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530130
131 /*
Varun Wadekar153982c2016-12-21 14:50:18 -0800132 * MCE propagates the VideoMem configuration values across the
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530133 * CCPLEX.
134 */
135 mce_update_gsc_videomem();
136 }
137}
138
139/*
140 * Secure the BL31 DRAM aperture.
141 *
142 * phys_base = physical base of TZDRAM aperture
143 * size_in_bytes = size of aperture in bytes
144 */
145void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
146{
Harvey Hsiehb7355412017-08-09 16:24:40 +0800147 uint32_t val;
148
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530149 /*
150 * Setup the Memory controller to allow only secure accesses to
151 * the TZDRAM carveout
152 */
153 INFO("Configuring TrustZone DRAM Memory Carveout\n");
154
155 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
156 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
157 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
158
159 /*
Harvey Hsiehc95802d2016-07-29 20:10:59 +0800160 * When TZ encryption enabled,
161 * We need setup TZDRAM before CPU to access TZ Carveout,
162 * otherwise CPU will fetch non-decrypted data.
Harvey Hsiehb7355412017-08-09 16:24:40 +0800163 * So save TZDRAM setting for restore by SC7 resume FW.
164 * Scratch registers map:
165 * RSV55_0 = CFG1[12:0] | CFG0[31:20]
166 * RSV55_1 = CFG3[1:0]
Harvey Hsiehc95802d2016-07-29 20:10:59 +0800167 */
168
Harvey Hsiehb7355412017-08-09 16:24:40 +0800169 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
Harvey Hsiehb7355412017-08-09 16:24:40 +0800170 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
171 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val);
172
173 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
174 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val);
Harvey Hsiehc95802d2016-07-29 20:10:59 +0800175
176 /*
Varun Wadekar153982c2016-12-21 14:50:18 -0800177 * MCE propagates the security configuration values across the
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530178 * CCPLEX.
179 */
180 mce_update_gsc_tzdram();
181}
182
183/*
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800184 * Secure the BL31 TZRAM aperture.
185 *
186 * phys_base = physical base of TZRAM aperture
187 * size_in_bytes = size of aperture in bytes
188 */
189void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
190{
Varun Wadekare6d43222016-05-25 16:35:04 -0700191 uint32_t index;
192 uint32_t total_128kb_blocks = size_in_bytes >> 17;
Varun Wadekar153982c2016-12-21 14:50:18 -0800193 uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800194 uint32_t val;
195
Varun Wadekar153982c2016-12-21 14:50:18 -0800196 INFO("Configuring TrustZone SRAM Memory Carveout\n");
197
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800198 /*
Varun Wadekare6d43222016-05-25 16:35:04 -0700199 * Reset the access configuration registers to restrict access
200 * to the TZRAM aperture
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800201 */
Varun Wadekar153982c2016-12-21 14:50:18 -0800202 for (index = MC_TZRAM_CLIENT_ACCESS_CFG0;
203 index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
204 index += 4U) {
Varun Wadekare6d43222016-05-25 16:35:04 -0700205 tegra_mc_write_32(index, 0);
Varun Wadekar153982c2016-12-21 14:50:18 -0800206 }
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800207
208 /*
Varun Wadekare6d43222016-05-25 16:35:04 -0700209 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
210 */
Varun Wadekar153982c2016-12-21 14:50:18 -0800211 assert((phys_base & (uint64_t)0xFFF) == 0U);
Varun Wadekare6d43222016-05-25 16:35:04 -0700212 tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
213 tegra_mc_write_32(MC_TZRAM_BASE_HI,
Varun Wadekar153982c2016-12-21 14:50:18 -0800214 (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800215
Varun Wadekare6d43222016-05-25 16:35:04 -0700216 /*
217 * Set the TZRAM size
218 *
219 * total size = (number of 128KB blocks) + (number of remaining 4KB
220 * blocks)
221 *
222 */
Varun Wadekar153982c2016-12-21 14:50:18 -0800223 val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
Varun Wadekare6d43222016-05-25 16:35:04 -0700224 total_128kb_blocks;
225 tegra_mc_write_32(MC_TZRAM_SIZE, val);
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800226
Varun Wadekare6d43222016-05-25 16:35:04 -0700227 /*
228 * Lock the configuration settings by disabling TZ-only lock
229 * and locking the configuration against any future changes
230 * at all.
231 */
232 val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
Anthony Zhou0844b972017-06-28 16:35:54 +0800233 val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
Varun Wadekar153982c2016-12-21 14:50:18 -0800234 val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
Varun Wadekare6d43222016-05-25 16:35:04 -0700235 tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800236
237 /*
Varun Wadekar153982c2016-12-21 14:50:18 -0800238 * MCE propagates the security configuration values across the
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800239 * CCPLEX.
240 */
241 mce_update_gsc_tzram();
242}
243
Varun Wadekar153982c2016-12-21 14:50:18 -0800244static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
245 uint64_t size_in_bytes)
246{
247 uint32_t index;
248 uint64_t total_128kb_blocks = size_in_bytes >> 17;
249 uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
250 uint64_t val;
251
252 /*
253 * Reset the access configuration registers to restrict access to
254 * old Videomem aperture
255 */
256 for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0;
257 index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
258 index += 4U) {
259 tegra_mc_write_32(index, 0);
260 }
261
262 /*
263 * Set the base. It must be 4k aligned, at least.
264 */
265 assert((phys_base & (uint64_t)0xFFF) == 0U);
266 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base);
267 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI,
268 (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK);
269
270 /*
271 * Set the aperture size
272 *
273 * total size = (number of 128KB blocks) + (number of remaining 4KB
274 * blocks)
275 *
276 */
277 val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
278 total_128kb_blocks);
279 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val);
280
281 /*
282 * Lock the configuration settings by enabling TZ-only lock and
283 * locking the configuration against any future changes from NS
284 * world.
285 */
286 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG,
287 (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT);
288
289 /*
290 * MCE propagates the GSC configuration values across the
291 * CCPLEX.
292 */
293}
294
295static void tegra_unlock_videomem_nonoverlap(void)
296{
297 /* Clear the base */
298 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0);
299 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0);
300
301 /* Clear the size */
302 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0);
303}
304
305static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
306 unsigned long long non_overlap_area_size)
307{
Varun Wadekar117a2e02017-08-03 11:40:34 -0700308 int ret;
309
Varun Wadekar153982c2016-12-21 14:50:18 -0800310 /*
311 * Map the NS memory first, clean it and then unmap it.
312 */
Varun Wadekar117a2e02017-08-03 11:40:34 -0700313 ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
Varun Wadekar153982c2016-12-21 14:50:18 -0800314 non_overlap_area_start, /* VA */
315 non_overlap_area_size, /* size */
316 MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
Varun Wadekar117a2e02017-08-03 11:40:34 -0700317 assert(ret == 0);
Varun Wadekar153982c2016-12-21 14:50:18 -0800318
319 zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
320 flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
321
Anthony Zhou0844b972017-06-28 16:35:54 +0800322 (void)mmap_remove_dynamic_region(non_overlap_area_start,
Varun Wadekar153982c2016-12-21 14:50:18 -0800323 non_overlap_area_size);
324}
325
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800326/*
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530327 * Program the Video Memory carveout region
328 *
329 * phys_base = physical base of aperture
330 * size_in_bytes = size of aperture in bytes
331 */
332void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
333{
Varun Wadekar153982c2016-12-21 14:50:18 -0800334 uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
335 uintptr_t vmem_end_new = phys_base + size_in_bytes;
Varun Wadekar153982c2016-12-21 14:50:18 -0800336 unsigned long long non_overlap_area_size;
Varun Wadekare60f1bf2016-02-17 10:10:50 -0800337
338 /*
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530339 * Setup the Memory controller to restrict CPU accesses to the Video
340 * Memory region
341 */
342 INFO("Configuring Video Memory Carveout\n");
343
Varun Wadekar153982c2016-12-21 14:50:18 -0800344 /*
345 * Configure Memory Controller directly for the first time.
346 */
347 if (video_mem_base == 0U)
348 goto done;
349
350 /*
351 * Lock the non overlapping memory being cleared so that other masters
352 * do not accidently write to it. The memory would be unlocked once
353 * the non overlapping region is cleared and the new memory
354 * settings take effect.
355 */
356 tegra_lock_videomem_nonoverlap(video_mem_base,
357 video_mem_size_mb << 20);
358
359 /*
360 * Clear the old regions now being exposed. The following cases
361 * can occur -
362 *
363 * 1. clear whole old region (no overlap with new region)
364 * 2. clear old sub-region below new base
365 * 3. clear old sub-region above new end
366 */
367 INFO("Cleaning previous Video Memory Carveout\n");
368
Anthony Zhou0844b972017-06-28 16:35:54 +0800369 if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
Varun Wadekar153982c2016-12-21 14:50:18 -0800370 tegra_clear_videomem(video_mem_base,
Anthony Zhou0844b972017-06-28 16:35:54 +0800371 (uint32_t)video_mem_size_mb << 20U);
Varun Wadekar153982c2016-12-21 14:50:18 -0800372 } else {
373 if (video_mem_base < phys_base) {
374 non_overlap_area_size = phys_base - video_mem_base;
Anthony Zhou0844b972017-06-28 16:35:54 +0800375 tegra_clear_videomem(video_mem_base,
376 (uint32_t)non_overlap_area_size);
Varun Wadekar153982c2016-12-21 14:50:18 -0800377 }
378 if (vmem_end_old > vmem_end_new) {
379 non_overlap_area_size = vmem_end_old - vmem_end_new;
Anthony Zhou0844b972017-06-28 16:35:54 +0800380 tegra_clear_videomem(vmem_end_new,
381 (uint32_t)non_overlap_area_size);
Varun Wadekar153982c2016-12-21 14:50:18 -0800382 }
383 }
384
385done:
386 /* program the Videomem aperture */
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530387 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
388 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
389 (uint32_t)(phys_base >> 32));
Varun Wadekar7058aee2016-04-25 09:01:46 -0700390 tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530391
Varun Wadekar153982c2016-12-21 14:50:18 -0800392 /* unlock the previous locked nonoverlapping aperture */
393 tegra_unlock_videomem_nonoverlap();
394
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530395 /* store new values */
396 video_mem_base = phys_base;
Varun Wadekar7058aee2016-04-25 09:01:46 -0700397 video_mem_size_mb = size_in_bytes >> 20;
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530398
399 /*
Varun Wadekar153982c2016-12-21 14:50:18 -0800400 * MCE propagates the VideoMem configuration values across the
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530401 * CCPLEX.
402 */
403 mce_update_gsc_videomem();
404}
Varun Wadekarc92050b2017-03-29 14:57:29 -0700405
406/*
407 * This feature exists only for v1 of the Tegra Memory Controller.
408 */
409void tegra_memctrl_disable_ahb_redirection(void)
410{
411 ; /* do nothing */
412}
Harvey Hsieh359be952017-08-21 15:01:53 +0800413
414void tegra_memctrl_clear_pending_interrupts(void)
415{
416 ; /* do nothing */
417}