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git01.mediatek.com / filogic / atf / b5664d35f73cf08b3f48b8c1522a37cbc1daa414 / . / include / drivers / ufs.h
blob: 3a4f1c780f7e837cd26dbc1b3abd5ffb9e0caeb3 [file] [log] [blame]
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800[diff] [blame]1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __UFS_H__
8#define __UFS_H__
9
10/* register map of UFSHCI */
11/* Controller Capabilities */
12#define CAP 0x00
13#define CAP_NUTRS_MASK 0x1F
14
15/* UFS Version */
16#define VER 0x08
17/* Host Controller Identification - Product ID */
18#define HCDDID 0x10
19/* Host Controller Identification Descriptor - Manufacturer ID */
20#define HCPMID 0x14
21/* Auto-Hibernate Idle Timer */
22#define AHIT 0x18
23/* Interrupt Status */
24#define IS 0x20
25/* Interrupt Enable */
26#define IE 0x24
27/* System Bus Fatal Error Status */
28#define UFS_INT_SBFES (1 << 17)
29/* Host Controller Fatal Error Status */
30#define UFS_INT_HCFES (1 << 16)
31/* UTP Error Status */
32#define UFS_INT_UTPES (1 << 12)
33/* Device Fatal Error Status */
34#define UFS_INT_DFES (1 << 11)
35/* UIC Command Completion Status */
36#define UFS_INT_UCCS (1 << 10)
37/* UTP Task Management Request Completion Status */
38#define UFS_INT_UTMRCS (1 << 9)
39/* UIC Link Startup Status */
40#define UFS_INT_ULSS (1 << 8)
41/* UIC Link Lost Status */
42#define UFS_INT_ULLS (1 << 7)
43/* UIC Hibernate Enter Status */
44#define UFS_INT_UHES (1 << 6)
45/* UIC Hibernate Exit Status */
46#define UFS_INT_UHXS (1 << 5)
47/* UIC Power Mode Status */
48#define UFS_INT_UPMS (1 << 4)
49/* UIC Test Mode Status */
50#define UFS_INT_UTMS (1 << 3)
51/* UIC Error */
52#define UFS_INT_UE (1 << 2)
53/* UIC DME_ENDPOINTRESET Indication */
54#define UFS_INT_UDEPRI (1 << 1)
55/* UTP Transfer Request Completion Status */
56#define UFS_INT_UTRCS (1 << 0)
57
58/* Host Controller Status */
59#define HCS 0x30
60#define HCS_UPMCRS_MASK (7 << 8)
61#define HCS_PWR_LOCAL (1 << 8)
62#define HCS_UCRDY (1 << 3)
63#define HCS_UTMRLRDY (1 << 2)
64#define HCS_UTRLRDY (1 << 1)
65#define HCS_DP (1 << 0)
66
67/* Host Controller Enable */
68#define HCE 0x34
69#define HCE_ENABLE 1
70
71/* Host UIC Error Code PHY Adapter Layer */
72#define UECPA 0x38
73/* Host UIC Error Code Data Link Layer */
74#define UECDL 0x3C
75/* Host UIC Error Code Network Layer */
76#define UECN 0x40
77/* Host UIC Error Code Transport Layer */
78#define UECT 0x44
79/* Host UIC Error Code */
80#define UECDME 0x48
81/* UTP Transfer Request Interrupt Aggregation Control Register */
82#define UTRIACR 0x4C
83#define UTRIACR_IAEN (1 << 31)
84#define UTRIACR_IAPWEN (1 << 24)
85#define UTRIACR_IASB (1 << 20)
86#define UTRIACR_CTR (1 << 16)
87#define UTRIACR_IACTH(x) (((x) & 0x1F) << 8)
88#define UTRIACR_IATOVAL(x) ((x) & 0xFF)
89
90/* UTP Transfer Request List Base Address */
91#define UTRLBA 0x50
92/* UTP Transfer Request List Base Address Upper 32-bits */
93#define UTRLBAU 0x54
94/* UTP Transfer Request List Door Bell Register */
95#define UTRLDBR 0x58
96/* UTP Transfer Request List Clear Register */
97#define UTRLCLR 0x5C
98/* UTP Transfer Request List Run Stop Register */
99#define UTRLRSR 0x60
100#define UTMRLBA 0x70
101#define UTMRLBAU 0x74
102#define UTMRLDBR 0x78
103#define UTMRLCLR 0x7C
104#define UTMRLRSR 0x80
105/* UIC Command */
106#define UICCMD 0x90
107/* UIC Command Argument 1 */
108#define UCMDARG1 0x94
109/* UIC Command Argument 2 */
110#define UCMDARG2 0x98
111/* UIC Command Argument 3 */
112#define UCMDARG3 0x9C
113
114#define UFS_BLOCK_SHIFT 12 /* 4KB */
115#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT)
116#define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1)
117#define UFS_MAX_LUNS 8
118
119/* UTP Transfer Request Descriptor */
120/* Command Type */
121#define CT_UFS_STORAGE 1
122#define CT_SCSI 0
123
124/* Data Direction */
125#define DD_OUT 2 /* Device --> Host */
126#define DD_IN 1 /* Host --> Device */
127#define DD_NO_DATA_TRANSFER 0
128
129#define UTP_TRD_SIZE 32
130
131/* Transaction Type */
132#define TRANS_TYPE_HD (1 << 7) /* E2ECRC */
133#define TRANS_TYPE_DD (1 << 6)
134#define TRANS_TYPE_CODE_MASK 0x3F
135#define QUERY_RESPONSE_UPIU (0x36 << 0)
136#define READY_TO_TRANSACTION_UPIU (0x31 << 0)
137#define DATA_IN_UPIU (0x22 << 0)
138#define RESPONSE_UPIU (0x21 << 0)
139#define NOP_IN_UPIU (0x20 << 0)
140#define QUERY_REQUEST_UPIU (0x16 << 0)
141#define DATA_OUT_UPIU (0x02 << 0)
142#define CMD_UPIU (0x01 << 0)
143#define NOP_OUT_UPIU (0x00 << 0)
144
145#define OCS_SUCCESS 0x0
146#define OCS_INVALID_FUNC_ATTRIBUTE 0x1
147#define OCS_MISMATCH_REQUEST_SIZE 0x2
148#define OCS_MISMATCH_RESPONSE_SIZE 0x3
149#define OCS_PEER_COMMUNICATION_FAILURE 0x4
150#define OCS_ABORTED 0x5
151#define OCS_FATAL_ERROR 0x6
152#define OCS_MASK 0xF
153
154/* UIC Command */
155#define DME_GET 0x01
156#define DME_SET 0x02
157#define DME_PEER_GET 0x03
158#define DME_PEER_SET 0x04
159#define DME_POWERON 0x10
160#define DME_POWEROFF 0x11
161#define DME_ENABLE 0x12
162#define DME_RESET 0x14
163#define DME_ENDPOINTRESET 0x15
164#define DME_LINKSTARTUP 0x16
165#define DME_HIBERNATE_ENTER 0x17
166#define DME_HIBERNATE_EXIT 0x18
167#define DME_TEST_MODE 0x1A
168
169#define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF)
170
171#define CONFIG_RESULT_CODE_MASK 0xFF
172
173#define CDBCMD_TEST_UNIT_READY 0x00
174#define CDBCMD_READ_6 0x08
175#define CDBCMD_WRITE_6 0x0A
176#define CDBCMD_START_STOP_UNIT 0x1B
177#define CDBCMD_READ_CAPACITY_10 0x25
178#define CDBCMD_READ_10 0x28
179#define CDBCMD_WRITE_10 0x2A
180#define CDBCMD_READ_16 0x88
181#define CDBCMD_WRITE_16 0x8A
182#define CDBCMD_READ_CAPACITY_16 0x9E
183#define CDBCMD_REPORT_LUNS 0xA0
184
185#define UPIU_FLAGS_R (1 << 6)
186#define UPIU_FLAGS_W (1 << 5)
187#define UPIU_FLAGS_ATTR_MASK (3 << 0)
188#define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */
189#define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */
190#define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */
191#define UPIU_FLAGS_ATTR_ACA (3 << 0)
192#define UPIU_FLAGS_O (1 << 6)
193#define UPIU_FLAGS_U (1 << 5)
194#define UPIU_FLAGS_D (1 << 4)
195
196#define QUERY_FUNC_STD_READ 0x01
197#define QUERY_FUNC_STD_WRITE 0x81
198
199#define QUERY_NOP 0x00
200#define QUERY_READ_DESC 0x01
201#define QUERY_WRITE_DESC 0x02
202#define QUERY_READ_ATTR 0x03
203#define QUERY_WRITE_ATTR 0x04
204#define QUERY_READ_FLAG 0x05
205#define QUERY_SET_FLAG 0x06
206#define QUERY_CLEAR_FLAG 0x07
207#define QUERY_TOGGLE_FLAG 0x08
208
209#define RW_WITHOUT_CACHE 0x18
210
211#define DESC_TYPE_DEVICE 0x00
212#define DESC_TYPE_CONFIGURATION 0x01
213#define DESC_TYPE_UNIT 0x02
214#define DESC_TYPE_INTERCONNECT 0x04
215#define DESC_TYPE_STRING 0x05
216
217#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
218#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
219
220#define DEVICE_DESCRIPTOR_LEN 0x40
221#define UNIT_DESCRIPTOR_LEN 0x23
222
223#define QUERY_RESP_SUCCESS 0x00
224#define QUERY_RESP_OPCODE 0xFE
225#define QUERY_RESP_GENERAL_FAIL 0xFF
226
227#define SENSE_KEY_NO_SENSE 0x00
228#define SENSE_KEY_RECOVERED_ERROR 0x01
229#define SENSE_KEY_NOT_READY 0x02
230#define SENSE_KEY_MEDIUM_ERROR 0x03
231#define SENSE_KEY_HARDWARE_ERROR 0x04
232#define SENSE_KEY_ILLEGAL_REQUEST 0x05
233#define SENSE_KEY_UNIT_ATTENTION 0x06
234#define SENSE_KEY_DATA_PROTECT 0x07
235#define SENSE_KEY_BLANK_CHECK 0x08
236#define SENSE_KEY_VENDOR_SPECIFIC 0x09
237#define SENSE_KEY_COPY_ABORTED 0x0A
238#define SENSE_KEY_ABORTED_COMMAND 0x0B
239#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
240#define SENSE_KEY_MISCOMPARE 0x0E
241
242#define SENSE_DATA_VALID 0x70
243#define SENSE_DATA_LENGTH 18
244
245#define READ_CAPACITY_LENGTH 8
246
247#define FLAG_DEVICE_INIT 0x01
248
249/* UFS Driver Flags */
250#define UFS_FLAGS_SKIPINIT (1 << 0)
251
252typedef struct sense_data {
253 uint8_t resp_code : 7;
254 uint8_t valid : 1;
255 uint8_t reserved0;
256 uint8_t sense_key : 4;
257 uint8_t reserved1 : 1;
258 uint8_t ili : 1;
259 uint8_t eom : 1;
260 uint8_t file_mark : 1;
261 uint8_t info[4];
262 uint8_t asl;
263 uint8_t cmd_spec_len[4];
264 uint8_t asc;
265 uint8_t ascq;
266 uint8_t fruc;
267 uint8_t sense_key_spec0 : 7;
268 uint8_t sksv : 1;
269 uint8_t sense_key_spec1;
270 uint8_t sense_key_spec2;
271} sense_data_t;
272
273/* UTP Transfer Request Descriptor */
274typedef struct utrd_header {
275 uint32_t reserved0 : 24;
276 uint32_t i : 1; /* interrupt */
277 uint32_t dd : 2; /* data direction */
278 uint32_t reserved1 : 1;
279 uint32_t ct : 4; /* command type */
280 uint32_t reserved2;
281 uint32_t ocs : 8; /* Overall Command Status */
282 uint32_t reserved3 : 24;
283 uint32_t reserved4;
284 uint32_t ucdba; /* aligned to 128-byte */
285 uint32_t ucdbau; /* Upper 32-bits */
286 uint32_t rul : 16; /* Response UPIU Length */
287 uint32_t ruo : 16; /* Response UPIU Offset */
288 uint32_t prdtl : 16; /* PRDT Length */
289 uint32_t prdto : 16; /* PRDT Offset */
290} utrd_header_t; /* 8 words with little endian */
291
292/* UTP Task Management Request Descriptor */
293typedef struct utp_utmrd {
294 /* 4 words with little endian */
295 uint32_t reserved0 : 24;
296 uint32_t i : 1; /* interrupt */
297 uint32_t reserved1 : 7;
298 uint32_t reserved2;
299 uint32_t ocs : 8; /* Overall Command Status */
300 uint32_t reserved3 : 24;
301 uint32_t reserved4;
302
303 /* followed by 8 words UPIU with big endian */
304
305 /* followed by 8 words Response UPIU with big endian */
306} utp_utmrd_t;
307
308/* NOP OUT UPIU */
309typedef struct nop_out_upiu {
310 uint8_t trans_type;
311 uint8_t flags;
312 uint8_t reserved0;
313 uint8_t task_tag;
314 uint8_t reserved1;
315 uint8_t reserved2;
316 uint8_t reserved3;
317 uint8_t reserved4;
318 uint8_t total_ehs_len;
319 uint8_t reserved5;
320 uint16_t data_segment_len;
321 uint32_t reserved6;
322 uint32_t reserved7;
323 uint32_t reserved8;
324 uint32_t reserved9;
325 uint32_t reserved10;
326 uint32_t e2ecrc;
327} nop_out_upiu_t; /* 36 bytes with big endian */
328
329/* NOP IN UPIU */
330typedef struct nop_in_upiu {
331 uint8_t trans_type;
332 uint8_t flags;
333 uint8_t reserved0;
334 uint8_t task_tag;
335 uint8_t reserved1;
336 uint8_t reserved2;
337 uint8_t response;
338 uint8_t reserved3;
339 uint8_t total_ehs_len;
340 uint8_t dev_info;
341 uint16_t data_segment_len;
342 uint32_t reserved4;
343 uint32_t reserved5;
344 uint32_t reserved6;
345 uint32_t reserved7;
346 uint32_t reserved8;
347 uint32_t e2ecrc;
348} nop_in_upiu_t; /* 36 bytes with big endian */
349
350/* Command UPIU */
351typedef struct cmd_upiu {
352 uint8_t trans_type;
353 uint8_t flags;
354 uint8_t lun;
355 uint8_t task_tag;
356 uint8_t cmd_set_type;
357 uint8_t reserved0;
358 uint8_t reserved1;
359 uint8_t reserved2;
360 uint8_t total_ehs_len;
361 uint8_t reserved3;
362 uint16_t data_segment_len;
363 uint32_t exp_data_trans_len;
364 /*
365 * A CDB has a fixed length of 16bytes or a variable length
366 * of between 12 and 260 bytes
367 */
368 uint8_t cdb[16]; /* little endian */
369} cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */
370
371typedef struct query_desc {
372 uint8_t opcode;
373 uint8_t idn;
374 uint8_t index;
375 uint8_t selector;
376 uint8_t reserved0[2];
377 uint16_t length;
378 uint32_t reserved2[2];
379} query_desc_t; /* 16 bytes with big endian */
380
381typedef struct query_flag {
382 uint8_t opcode;
383 uint8_t idn;
384 uint8_t index;
385 uint8_t selector;
386 uint8_t reserved0[7];
387 uint8_t value;
388 uint32_t reserved8;
389} query_flag_t; /* 16 bytes with big endian */
390
391typedef struct query_attr {
392 uint8_t opcode;
393 uint8_t idn;
394 uint8_t index;
395 uint8_t selector;
396 uint8_t reserved0[4];
397 uint32_t value; /* little endian */
398 uint32_t reserved4;
399} query_attr_t; /* 16 bytes with big endian except for value */
400
401/* Query Request UPIU */
402typedef struct query_upiu {
403 uint8_t trans_type;
404 uint8_t flags;
405 uint8_t reserved0;
406 uint8_t task_tag;
407 uint8_t reserved1;
408 uint8_t query_func;
409 uint8_t reserved2;
410 uint8_t reserved3;
411 uint8_t total_ehs_len;
412 uint8_t reserved4;
413 uint16_t data_segment_len;
414 /* Transaction Specific Fields */
415 union {
416 query_desc_t desc;
417 query_flag_t flag;
418 query_attr_t attr;
419 } ts;
420 uint32_t reserved5;
421} query_upiu_t; /* 32 bytes with big endian */
422
423/* Query Response UPIU */
424typedef struct query_resp_upiu {
425 uint8_t trans_type;
426 uint8_t flags;
427 uint8_t reserved0;
428 uint8_t task_tag;
429 uint8_t reserved1;
430 uint8_t query_func;
431 uint8_t query_resp;
432 uint8_t reserved2;
433 uint8_t total_ehs_len;
434 uint8_t dev_info;
435 uint16_t data_segment_len;
436 union {
437 query_desc_t desc;
438 query_flag_t flag;
439 query_attr_t attr;
440 } ts;
441 uint32_t reserved3;
442} query_resp_upiu_t; /* 32 bytes with big endian */
443
444/* Response UPIU */
445typedef struct resp_upiu {
446 uint8_t trans_type;
447 uint8_t flags;
448 uint8_t lun;
449 uint8_t task_tag;
450 uint8_t cmd_set_type;
451 uint8_t reserved0;
452 uint8_t reserved1;
453 uint8_t status;
454 uint8_t total_ehs_len;
455 uint8_t dev_info;
456 uint16_t data_segment_len;
457 uint32_t res_trans_cnt; /* Residual Transfer Count */
458 uint32_t reserved2[4];
459 uint16_t sense_data_len;
460 union {
461 uint8_t sense_data[18];
462 sense_data_t sense;
463 } sd;
464} resp_upiu_t; /* 52 bytes with big endian */
465
466typedef struct cmd_info {
467 uintptr_t buf;
468 size_t length;
469 int lba;
470 uint8_t op;
471 uint8_t direction;
472 uint8_t lun;
473} cmd_info_t;
474
475typedef struct utp_utrd {
476 uintptr_t header; /* utrd_header_t */
477 uintptr_t upiu;
478 uintptr_t resp_upiu;
479 uintptr_t prdt;
480 size_t size_upiu;
481 size_t size_resp_upiu;
482 size_t size_prdt;
483 int task_tag;
484} utp_utrd_t;
485
486/* Physical Region Description Table */
487typedef struct prdt {
488 uint32_t dba; /* Data Base Address */
489 uint32_t dbau; /* Data Base Address Upper 32-bits */
490 uint32_t reserved0;
491 uint32_t dbc : 18; /* Data Byte Count */
492 uint32_t reserved1 : 14;
493} prdt_t;
494
495typedef struct uic_cmd {
496 uint32_t op;
497 uint32_t arg1;
498 uint32_t arg2;
499 uint32_t arg3;
500} uic_cmd_t;
501
502typedef struct ufs_params {
503 uintptr_t reg_base;
504 uintptr_t desc_base;
505 size_t desc_size;
506 unsigned long flags;
507} ufs_params_t;
508
509typedef struct ufs_ops {
510 int (*phy_init)(ufs_params_t *params);
511 int (*phy_set_pwr_mode)(ufs_params_t *params);
512} ufs_ops_t;
513
514int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd);
515int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val);
516int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val);
517
518unsigned int ufs_read_attr(int idn);
519void ufs_write_attr(int idn, unsigned int value);
520unsigned int ufs_read_flag(int idn);
521void ufs_set_flag(int idn);
522void ufs_clear_flag(int idn);
523void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size);
524void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size);
525size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size);
526size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size);
527int ufs_init(const ufs_ops_t *ops, ufs_params_t *params);
528
529#endif /* __UFS_H__ */