Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include "../fpga_def.h" |
| 12 | |
| 13 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 14 | |
| 15 | #define PLATFORM_LINKER_ARCH aarch64 |
| 16 | |
| 17 | #define PLATFORM_STACK_SIZE UL(0x800) |
| 18 | |
| 19 | #define CACHE_WRITEBACK_SHIFT U(6) |
| 20 | #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) |
| 21 | |
| 22 | #define PLATFORM_CORE_COUNT \ |
| 23 | (FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU) |
| 24 | |
| 25 | #define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \ |
| 26 | PLATFORM_CORE_COUNT) + 1 |
| 27 | |
| 28 | #define BL31_BASE UL(0x80000000) |
| 29 | #define BL31_LIMIT UL(0x80100000) |
| 30 | |
Oliver Swede | b51da81 | 2019-12-03 14:08:21 +0000 | [diff] [blame^] | 31 | #define GICD_BASE 0x30000000 |
| 32 | #define GICR_BASE 0x30040000 |
| 33 | |
| 34 | #define PLAT_SDEI_NORMAL_PRI 0x70 |
| 35 | |
| 36 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 37 | |
| 38 | #define ARM_IRQ_SEC_SGI_0 8 |
| 39 | #define ARM_IRQ_SEC_SGI_1 9 |
| 40 | #define ARM_IRQ_SEC_SGI_2 10 |
| 41 | #define ARM_IRQ_SEC_SGI_3 11 |
| 42 | #define ARM_IRQ_SEC_SGI_4 12 |
| 43 | #define ARM_IRQ_SEC_SGI_5 13 |
| 44 | #define ARM_IRQ_SEC_SGI_6 14 |
| 45 | #define ARM_IRQ_SEC_SGI_7 15 |
| 46 | |
| 47 | /* |
| 48 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 49 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 50 | * as Group 0 interrupts. |
| 51 | */ |
| 52 | #define PLATFORM_G1S_PROPS(grp) \ |
| 53 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 54 | GIC_INTR_CFG_LEVEL), \ |
| 55 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 56 | GIC_INTR_CFG_EDGE), \ |
| 57 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 58 | GIC_INTR_CFG_EDGE), \ |
| 59 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 60 | GIC_INTR_CFG_EDGE), \ |
| 61 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 62 | GIC_INTR_CFG_EDGE), \ |
| 63 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 64 | GIC_INTR_CFG_EDGE), \ |
| 65 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 66 | GIC_INTR_CFG_EDGE) |
| 67 | |
| 68 | #define PLATFORM_G0_PROPS(grp) \ |
| 69 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ |
| 70 | GIC_INTR_CFG_EDGE), \ |
| 71 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 72 | GIC_INTR_CFG_EDGE) |
| 73 | |
| 74 | #define PLAT_MAX_RET_STATE 1 |
| 75 | #define PLAT_MAX_OFF_STATE 2 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 76 | |
| 77 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 |
| 78 | |
Oliver Swede | 6e86c5a | 2019-12-02 13:21:52 +0000 | [diff] [blame] | 79 | #define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 |
| 80 | #define PLAT_FPGA_HOLD_STATE_WAIT 0 |
| 81 | #define PLAT_FPGA_HOLD_STATE_GO 1 |
| 82 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 83 | #define PLAT_FPGA_CONSOLE_BAUDRATE 38400 |
| 84 | |
| 85 | #endif |