Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited. All rights reserved. |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 3 | * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef TRAP_HANDLE_H |
| 9 | #define TRAP_HANDLE_H |
| 10 | |
| 11 | #include <stdbool.h> |
| 12 | #include <context.h> |
| 13 | |
| 14 | #define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL |
| 15 | #define ISS_SYSREG_REG_MASK 0x0003e0UL |
| 16 | #define ISS_SYSREG_REG_SHIFT 5U |
| 17 | #define ISS_SYSREG_DIRECTION_MASK 0x000001UL |
| 18 | |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 19 | #define ISS_SYSREG_OPCODE_RNDR 0x30c808U |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 20 | #define ISS_SYSREG_OPCODE_IMPDEF 0x303c00U |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 21 | #define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U |
| 22 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 23 | #define TRAP_RET_UNHANDLED -1 |
| 24 | #define TRAP_RET_REPEAT 0 |
| 25 | #define TRAP_RET_CONTINUE 1 |
| 26 | |
| 27 | #ifndef __ASSEMBLER__ |
| 28 | static inline unsigned int get_sysreg_iss_rt(uint64_t esr) |
| 29 | { |
| 30 | return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT; |
| 31 | } |
| 32 | |
| 33 | static inline bool is_sysreg_iss_write(uint64_t esr) |
| 34 | { |
| 35 | return !(esr & ISS_SYSREG_DIRECTION_MASK); |
| 36 | } |
| 37 | |
| 38 | /** |
| 39 | * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs |
| 40 | * @esr_el3: The content of ESR_EL3, containing the trap syndrome information |
| 41 | * @ctx: Pointer to the lower EL context, containing saved registers |
| 42 | * |
| 43 | * Called by the exception handler when a synchronous trap identifies as a |
| 44 | * system register trap (EC=0x18). ESR contains the encoding of the op[x] and |
| 45 | * CRm/CRn fields, to identify the system register, and the target/source |
| 46 | * GPR plus the direction (MRS/MSR). The lower EL's context can be altered |
| 47 | * by the function, to inject back the result of the emulation. |
| 48 | * |
| 49 | * Return: indication how to proceed with the trap: |
| 50 | * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic |
| 51 | * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction |
| 52 | * (repeating it) |
| 53 | * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction |
| 54 | * (continuing after it) |
| 55 | */ |
| 56 | int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); |
| 57 | |
Manish Pandey | 067087f | 2023-12-08 20:13:29 +0000 | [diff] [blame] | 58 | /* Handler for injecting UNDEF exception to lower EL */ |
| 59 | void inject_undef64(cpu_context_t *ctx); |
| 60 | |
Arvind Ram Prakash | df8200d | 2024-02-20 11:35:27 -0600 | [diff] [blame] | 61 | u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el); |
| 62 | |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 63 | /* Prototypes for system register emulation handlers provided by platforms. */ |
Varun Wadekar | 0a46eb1 | 2023-04-13 21:06:18 +0100 | [diff] [blame] | 64 | int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx); |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 65 | int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx); |
| 66 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 67 | #endif /* __ASSEMBLER__ */ |
| 68 | |
| 69 | #endif |