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Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +02001/*
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +09002 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +02007#include <stdint.h>
8#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <common/debug.h>
11#include <lib/mmio.h>
12
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020013#include "cpg_registers.h"
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090014#include "rcar_def.h"
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020015#include "rcar_private.h"
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090016#include "rpc_registers.h"
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020017
18#define MSTPSR9_RPC_BIT (0x00020000U)
19#define RPC_CMNCR_MD_BIT (0x80000000U)
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090020#define RPC_PHYCNT_CAL BIT(31)
21#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
22#define RPC_PHYCNT_STRTIM (0x7 << 15UL)
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020023
24static void rpc_enable(void)
25{
26 /* Enable clock supply to RPC. */
27 mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
28}
29
30static void rpc_setup(void)
31{
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090032 uint32_t product, cut, reg, phy_strtim;
33
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020034 if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
35 mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090036
Marek Vasut9cadc782019-08-06 19:13:22 +020037 product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
38 cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090039
Marek Vasut9cadc782019-08-06 19:13:22 +020040 if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
Toshiyuki Ogasahara46c7c422019-05-20 11:23:48 +090041 phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
42 else
43 phy_strtim = RPC_PHYCNT_STRTIM;
44
45 reg = mmio_read_32(RPC_PHYCNT);
46 reg &= ~RPC_PHYCNT_STRTIM;
47 reg |= phy_strtim;
48 mmio_write_32(RPC_PHYCNT, reg);
49 reg |= RPC_PHYCNT_CAL;
50 mmio_write_32(RPC_PHYCNT, reg);
Jorge Ramirez-Ortizd26a7222018-09-23 09:41:39 +020051}
52
53void rcar_rpc_init(void)
54{
55 rpc_enable();
56 rpc_setup();
57}