Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 1 | /* |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <string.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | |
| 10 | #include <common/debug.h> |
| 11 | #include <lib/mmio.h> |
| 12 | |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 13 | #include "cpg_registers.h" |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 14 | #include "rcar_def.h" |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 15 | #include "rcar_private.h" |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 16 | #include "rpc_registers.h" |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 17 | |
| 18 | #define MSTPSR9_RPC_BIT (0x00020000U) |
| 19 | #define RPC_CMNCR_MD_BIT (0x80000000U) |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 20 | #define RPC_PHYCNT_CAL BIT(31) |
| 21 | #define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL) |
| 22 | #define RPC_PHYCNT_STRTIM (0x7 << 15UL) |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 23 | |
| 24 | static void rpc_enable(void) |
| 25 | { |
| 26 | /* Enable clock supply to RPC. */ |
| 27 | mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT); |
| 28 | } |
| 29 | |
| 30 | static void rpc_setup(void) |
| 31 | { |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 32 | uint32_t product, cut, reg, phy_strtim; |
| 33 | |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 34 | if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT) |
| 35 | mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT); |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 36 | |
Marek Vasut | 9cadc78 | 2019-08-06 19:13:22 +0200 | [diff] [blame] | 37 | product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK; |
| 38 | cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 39 | |
Marek Vasut | 9cadc78 | 2019-08-06 19:13:22 +0200 | [diff] [blame] | 40 | if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30)) |
Toshiyuki Ogasahara | 46c7c42 | 2019-05-20 11:23:48 +0900 | [diff] [blame] | 41 | phy_strtim = RPC_PHYCNT_STRTIM_M3V1; |
| 42 | else |
| 43 | phy_strtim = RPC_PHYCNT_STRTIM; |
| 44 | |
| 45 | reg = mmio_read_32(RPC_PHYCNT); |
| 46 | reg &= ~RPC_PHYCNT_STRTIM; |
| 47 | reg |= phy_strtim; |
| 48 | mmio_write_32(RPC_PHYCNT, reg); |
| 49 | reg |= RPC_PHYCNT_CAL; |
| 50 | mmio_write_32(RPC_PHYCNT, reg); |
Jorge Ramirez-Ortiz | d26a722 | 2018-09-23 09:41:39 +0200 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | void rcar_rpc_init(void) |
| 54 | { |
| 55 | rpc_enable(); |
| 56 | rpc_setup(); |
| 57 | } |