Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018-2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <bl31/interrupt_mgmt.h> |
| 12 | #include <caam.h> |
| 13 | #include <cassert.h> |
| 14 | #include <ccn.h> |
| 15 | #include <common/debug.h> |
| 16 | #include <dcfg.h> |
| 17 | #ifdef I2C_INIT |
| 18 | #include <i2c.h> |
| 19 | #endif |
| 20 | #include <lib/mmio.h> |
| 21 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 22 | #include <ls_interconnect.h> |
| 23 | #ifdef POLICY_FUSE_PROVISION |
| 24 | #include <nxp_gpio.h> |
| 25 | #endif |
| 26 | #if TRUSTED_BOARD_BOOT |
| 27 | #include <nxp_smmu.h> |
| 28 | #endif |
| 29 | #include <nxp_timer.h> |
| 30 | #include <plat_console.h> |
| 31 | #include <plat_gic.h> |
| 32 | #include <plat_tzc400.h> |
| 33 | #include <pmu.h> |
| 34 | #if defined(NXP_SFP_ENABLED) |
| 35 | #include <sfp.h> |
| 36 | #endif |
| 37 | |
| 38 | #include <errata.h> |
| 39 | #include <ls_interrupt_mgmt.h> |
Jiafei Pan | 566e7d9 | 2022-10-11 14:58:18 +0800 | [diff] [blame] | 40 | #ifdef CONFIG_OCRAM_ECC_EN |
| 41 | #include <ocram.h> |
| 42 | #endif |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 43 | #include "plat_common.h" |
| 44 | #ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA |
| 45 | #include <plat_nv_storage.h> |
| 46 | #endif |
| 47 | #ifdef NXP_WARM_BOOT |
| 48 | #include <plat_warm_rst.h> |
| 49 | #endif |
| 50 | #include "platform_def.h" |
| 51 | #include "soc.h" |
| 52 | |
| 53 | static struct soc_type soc_list[] = { |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame] | 54 | /* SoC LX2160A */ |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 55 | SOC_ENTRY(LX2160A, LX2160A, 8, 2), |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame] | 56 | SOC_ENTRY(LX2160E, LX2160E, 8, 2), |
| 57 | SOC_ENTRY(LX2160C, LX2160C, 8, 2), |
| 58 | SOC_ENTRY(LX2160N, LX2160N, 8, 2), |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 59 | SOC_ENTRY(LX2080A, LX2080A, 8, 1), |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame] | 60 | SOC_ENTRY(LX2080E, LX2080E, 8, 1), |
| 61 | SOC_ENTRY(LX2080C, LX2080C, 8, 1), |
| 62 | SOC_ENTRY(LX2080N, LX2080N, 8, 1), |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 63 | SOC_ENTRY(LX2120A, LX2120A, 6, 2), |
Jiafei Pan | 616a94a | 2022-06-10 17:26:34 +0800 | [diff] [blame] | 64 | SOC_ENTRY(LX2120E, LX2120E, 6, 2), |
| 65 | SOC_ENTRY(LX2120C, LX2120C, 6, 2), |
| 66 | SOC_ENTRY(LX2120N, LX2120N, 6, 2), |
| 67 | /* SoC LX2162A */ |
| 68 | SOC_ENTRY(LX2162A, LX2162A, 8, 2), |
| 69 | SOC_ENTRY(LX2162E, LX2162E, 8, 2), |
| 70 | SOC_ENTRY(LX2162C, LX2162C, 8, 2), |
| 71 | SOC_ENTRY(LX2162N, LX2162N, 8, 2), |
| 72 | SOC_ENTRY(LX2082A, LX2082A, 8, 1), |
| 73 | SOC_ENTRY(LX2082E, LX2082E, 8, 1), |
| 74 | SOC_ENTRY(LX2082C, LX2082C, 8, 1), |
| 75 | SOC_ENTRY(LX2082N, LX2082N, 8, 1), |
| 76 | SOC_ENTRY(LX2122A, LX2122A, 6, 2), |
| 77 | SOC_ENTRY(LX2122E, LX2122E, 6, 2), |
| 78 | SOC_ENTRY(LX2122C, LX2122C, 6, 2), |
| 79 | SOC_ENTRY(LX2122N, LX2122N, 6, 2), |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | static dcfg_init_info_t dcfg_init_data = { |
| 83 | .g_nxp_dcfg_addr = NXP_DCFG_ADDR, |
| 84 | .nxp_sysclk_freq = NXP_SYSCLK_FREQ, |
| 85 | .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, |
| 86 | .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, |
| 87 | }; |
| 88 | static const unsigned char master_to_6rn_id_map[] = { |
| 89 | PLAT_6CLUSTER_TO_CCN_ID_MAP |
| 90 | }; |
| 91 | |
| 92 | static const unsigned char master_to_rn_id_map[] = { |
| 93 | PLAT_CLUSTER_TO_CCN_ID_MAP |
| 94 | }; |
| 95 | |
| 96 | CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS, |
| 97 | assert_invalid_cluster_count_for_ccn_variant); |
| 98 | |
| 99 | static const ccn_desc_t plat_six_cluster_ccn_desc = { |
| 100 | .periphbase = NXP_CCN_ADDR, |
| 101 | .num_masters = ARRAY_SIZE(master_to_6rn_id_map), |
| 102 | .master_to_rn_id_map = master_to_6rn_id_map |
| 103 | }; |
| 104 | |
| 105 | static const ccn_desc_t plat_ccn_desc = { |
| 106 | .periphbase = NXP_CCN_ADDR, |
| 107 | .num_masters = ARRAY_SIZE(master_to_rn_id_map), |
| 108 | .master_to_rn_id_map = master_to_rn_id_map |
| 109 | }; |
| 110 | |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 111 | /****************************************************************************** |
| 112 | * Function returns the base counter frequency |
| 113 | * after reading the first entry at CNTFID0 (0x20 offset). |
| 114 | * |
| 115 | * Function is used by: |
| 116 | * 1. ARM common code for PSCI management. |
| 117 | * 2. ARM Generic Timer init. |
| 118 | * |
| 119 | *****************************************************************************/ |
| 120 | unsigned int plat_get_syscnt_freq2(void) |
| 121 | { |
| 122 | unsigned int counter_base_frequency; |
| 123 | /* |
| 124 | * Below register specifies the base frequency of the system counter. |
| 125 | * As per NXP Board Manuals: |
| 126 | * The system counter always works with SYS_REF_CLK/4 frequency clock. |
| 127 | * |
| 128 | * |
| 129 | */ |
| 130 | counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); |
| 131 | |
| 132 | return counter_base_frequency; |
| 133 | } |
| 134 | |
| 135 | #ifdef IMAGE_BL2 |
| 136 | |
| 137 | #ifdef POLICY_FUSE_PROVISION |
| 138 | static gpio_init_info_t gpio_init_data = { |
| 139 | .gpio1_base_addr = NXP_GPIO1_ADDR, |
| 140 | .gpio2_base_addr = NXP_GPIO2_ADDR, |
| 141 | .gpio3_base_addr = NXP_GPIO3_ADDR, |
| 142 | .gpio4_base_addr = NXP_GPIO4_ADDR, |
| 143 | }; |
| 144 | #endif |
| 145 | |
| 146 | static void soc_interconnect_config(void) |
| 147 | { |
| 148 | unsigned long long val = 0x0U; |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 149 | uint8_t num_clusters, cores_per_cluster; |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 150 | |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 151 | get_cluster_info(soc_list, ARRAY_SIZE(soc_list), |
| 152 | &num_clusters, &cores_per_cluster); |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 153 | |
| 154 | if (num_clusters == 6U) { |
| 155 | ccn_init(&plat_six_cluster_ccn_desc); |
| 156 | } else { |
| 157 | ccn_init(&plat_ccn_desc); |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * Enable Interconnect coherency for the primary CPU's cluster. |
| 162 | */ |
| 163 | plat_ls_interconnect_enter_coherency(num_clusters); |
| 164 | |
| 165 | val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET); |
| 166 | val |= (1 << 17); |
| 167 | ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val); |
| 168 | |
| 169 | /* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */ |
| 170 | val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET); |
| 171 | val |= (1 << 17); |
| 172 | ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val); |
| 173 | |
| 174 | val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); |
| 175 | val |= SERIALIZE_DEV_nGnRnE_WRITES; |
| 176 | ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); |
| 177 | |
| 178 | val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); |
| 179 | val &= ~(ENABLE_RESERVE_BIT53); |
| 180 | val |= SERIALIZE_DEV_nGnRnE_WRITES; |
| 181 | ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); |
| 182 | |
| 183 | val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET); |
| 184 | val &= ~(HNI_POS_EN); |
| 185 | ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val); |
| 186 | |
| 187 | val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET); |
| 188 | val &= ~(HNI_POS_EN); |
| 189 | ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val); |
| 190 | |
| 191 | val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); |
| 192 | val &= ~(POS_EARLY_WR_COMP_EN); |
| 193 | ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); |
| 194 | |
| 195 | val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); |
| 196 | val &= ~(POS_EARLY_WR_COMP_EN); |
| 197 | ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); |
| 198 | |
| 199 | #if POLICY_PERF_WRIOP |
| 200 | uint16_t wriop_rni = 0U; |
| 201 | |
| 202 | if (POLICY_PERF_WRIOP == 1) { |
| 203 | wriop_rni = 7U; |
| 204 | } else if (POLICY_PERF_WRIOP == 2) { |
| 205 | wriop_rni = 23U; |
| 206 | } else { |
| 207 | ERROR("Incorrect WRIOP selected.\n"); |
| 208 | panic(); |
| 209 | } |
| 210 | |
| 211 | val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni, |
| 212 | SA_AUX_CTRL_REG_OFFSET); |
| 213 | val |= ENABLE_WUO; |
| 214 | ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET, |
| 215 | val); |
| 216 | #else |
| 217 | val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET); |
| 218 | val |= ENABLE_WUO; |
| 219 | ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val); |
| 220 | #endif |
| 221 | } |
| 222 | |
| 223 | |
| 224 | void soc_preload_setup(void) |
| 225 | { |
| 226 | dram_regions_info_t *info_dram_regions = get_dram_regions_info(); |
| 227 | #if defined(NXP_WARM_BOOT) |
| 228 | bool warm_reset = is_warm_boot(); |
| 229 | #endif |
| 230 | info_dram_regions->total_dram_size = |
| 231 | #if defined(NXP_WARM_BOOT) |
| 232 | init_ddr(warm_reset); |
| 233 | #else |
| 234 | init_ddr(); |
| 235 | #endif |
| 236 | } |
| 237 | |
| 238 | /******************************************************************************* |
| 239 | * This function implements soc specific erratas |
| 240 | * This is called before DDR is initialized or MMU is enabled |
| 241 | ******************************************************************************/ |
| 242 | void soc_early_init(void) |
| 243 | { |
Jiafei Pan | 566e7d9 | 2022-10-11 14:58:18 +0800 | [diff] [blame] | 244 | #ifdef CONFIG_OCRAM_ECC_EN |
| 245 | ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); |
| 246 | #endif |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 247 | dcfg_init(&dcfg_init_data); |
| 248 | #ifdef POLICY_FUSE_PROVISION |
| 249 | gpio_init(&gpio_init_data); |
| 250 | sec_init(NXP_CAAM_ADDR); |
| 251 | #endif |
| 252 | #if LOG_LEVEL > 0 |
| 253 | /* Initialize the console to provide early debug support */ |
| 254 | plat_console_init(NXP_CONSOLE_ADDR, |
| 255 | NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); |
| 256 | #endif |
| 257 | |
| 258 | enable_timer_base_to_cluster(NXP_PMU_ADDR); |
| 259 | soc_interconnect_config(); |
| 260 | |
| 261 | enum boot_device dev = get_boot_dev(); |
| 262 | /* Mark the buffer for SD in OCRAM as non secure. |
| 263 | * The buffer is assumed to be at end of OCRAM for |
| 264 | * the logic below to calculate TZPC programming |
| 265 | */ |
| 266 | if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { |
| 267 | /* Calculate the region in OCRAM which is secure |
| 268 | * The buffer for SD needs to be marked non-secure |
| 269 | * to allow SD to do DMA operations on it |
| 270 | */ |
| 271 | uint32_t secure_region = (NXP_OCRAM_SIZE |
| 272 | - NXP_SD_BLOCK_BUF_SIZE); |
| 273 | uint32_t mask = secure_region/TZPC_BLOCK_SIZE; |
| 274 | |
| 275 | mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); |
| 276 | |
| 277 | /* Add the entry for buffer in MMU Table */ |
| 278 | mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, |
| 279 | NXP_SD_BLOCK_BUF_SIZE, |
| 280 | MT_DEVICE | MT_RW | MT_NS); |
| 281 | } |
| 282 | |
Jiafei Pan | 942f567 | 2021-07-20 15:21:06 +0800 | [diff] [blame] | 283 | soc_errata(); |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 284 | |
| 285 | #if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION) |
| 286 | sfp_init(NXP_SFP_ADDR); |
| 287 | #endif |
| 288 | |
| 289 | #if TRUSTED_BOARD_BOOT |
| 290 | uint32_t mode; |
| 291 | |
| 292 | /* For secure boot disable SMMU. |
| 293 | * Later when platform security policy comes in picture, |
| 294 | * this might get modified based on the policy |
| 295 | */ |
| 296 | if (check_boot_mode_secure(&mode) == true) { |
| 297 | bypass_smmu(NXP_SMMU_ADDR); |
| 298 | } |
| 299 | |
| 300 | /* For Mbedtls currently crypto is not supported via CAAM |
| 301 | * enable it when that support is there. In tbbr.mk |
| 302 | * the CAAM_INTEG is set as 0. |
| 303 | */ |
| 304 | |
| 305 | #ifndef MBEDTLS_X509 |
| 306 | /* Initialize the crypto accelerator if enabled */ |
| 307 | if (is_sec_enabled() == false) |
| 308 | INFO("SEC is disabled.\n"); |
| 309 | else |
| 310 | sec_init(NXP_CAAM_ADDR); |
| 311 | #endif |
| 312 | #endif |
| 313 | |
| 314 | /* |
| 315 | * Initialize system level generic timer for Layerscape Socs. |
| 316 | */ |
| 317 | delay_timer_init(NXP_TIMER_ADDR); |
| 318 | i2c_init(NXP_I2C_ADDR); |
| 319 | } |
| 320 | |
| 321 | void soc_bl2_prepare_exit(void) |
| 322 | { |
| 323 | #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) |
| 324 | set_sfp_wr_disable(); |
| 325 | #endif |
| 326 | } |
| 327 | |
| 328 | /***************************************************************************** |
| 329 | * This function returns the boot device based on RCW_SRC |
| 330 | ****************************************************************************/ |
| 331 | enum boot_device get_boot_dev(void) |
| 332 | { |
| 333 | enum boot_device src = BOOT_DEVICE_NONE; |
| 334 | uint32_t porsr1; |
| 335 | uint32_t rcw_src; |
| 336 | |
| 337 | porsr1 = read_reg_porsr1(); |
| 338 | |
| 339 | rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; |
| 340 | |
| 341 | switch (rcw_src) { |
| 342 | case FLEXSPI_NOR: |
| 343 | src = BOOT_DEVICE_FLEXSPI_NOR; |
| 344 | INFO("RCW BOOT SRC is FLEXSPI NOR\n"); |
| 345 | break; |
| 346 | case FLEXSPI_NAND2K_VAL: |
| 347 | case FLEXSPI_NAND4K_VAL: |
| 348 | INFO("RCW BOOT SRC is FLEXSPI NAND\n"); |
| 349 | src = BOOT_DEVICE_FLEXSPI_NAND; |
| 350 | break; |
| 351 | case SDHC1_VAL: |
| 352 | src = BOOT_DEVICE_EMMC; |
| 353 | INFO("RCW BOOT SRC is SD\n"); |
| 354 | break; |
| 355 | case SDHC2_VAL: |
| 356 | src = BOOT_DEVICE_SDHC2_EMMC; |
| 357 | INFO("RCW BOOT SRC is EMMC\n"); |
| 358 | break; |
| 359 | default: |
| 360 | break; |
| 361 | } |
| 362 | |
| 363 | return src; |
| 364 | } |
| 365 | |
| 366 | |
| 367 | void soc_mem_access(void) |
| 368 | { |
| 369 | const devdisr5_info_t *devdisr5_info = get_devdisr5_info(); |
| 370 | dram_regions_info_t *info_dram_regions = get_dram_regions_info(); |
| 371 | struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; |
| 372 | int dram_idx, index = 0U; |
| 373 | |
| 374 | for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; |
| 375 | dram_idx++) { |
| 376 | if (info_dram_regions->region[dram_idx].size == 0) { |
| 377 | ERROR("DDR init failure, or"); |
| 378 | ERROR("DRAM regions not populated correctly.\n"); |
| 379 | break; |
| 380 | } |
| 381 | |
| 382 | index = populate_tzc400_reg_list(tzc400_reg_list, |
| 383 | dram_idx, index, |
| 384 | info_dram_regions->region[dram_idx].addr, |
| 385 | info_dram_regions->region[dram_idx].size, |
| 386 | NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); |
| 387 | } |
| 388 | |
| 389 | if (devdisr5_info->ddrc1_present != 0) { |
| 390 | INFO("DDR Controller 1.\n"); |
| 391 | mem_access_setup(NXP_TZC_ADDR, index, |
| 392 | tzc400_reg_list); |
| 393 | mem_access_setup(NXP_TZC3_ADDR, index, |
| 394 | tzc400_reg_list); |
| 395 | } |
| 396 | if (devdisr5_info->ddrc2_present != 0) { |
| 397 | INFO("DDR Controller 2.\n"); |
| 398 | mem_access_setup(NXP_TZC2_ADDR, index, |
| 399 | tzc400_reg_list); |
| 400 | mem_access_setup(NXP_TZC4_ADDR, index, |
| 401 | tzc400_reg_list); |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | #else |
| 406 | const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2}; |
| 407 | |
| 408 | CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, |
| 409 | assert_invalid_lx2160a_cluster_count); |
| 410 | |
| 411 | /****************************************************************************** |
| 412 | * This function returns the SoC topology |
| 413 | ****************************************************************************/ |
| 414 | |
| 415 | const unsigned char *plat_get_power_domain_tree_desc(void) |
| 416 | { |
| 417 | |
| 418 | return _power_domain_tree_desc; |
| 419 | } |
| 420 | |
| 421 | /******************************************************************************* |
| 422 | * This function returns the core count within the cluster corresponding to |
| 423 | * `mpidr`. |
| 424 | ******************************************************************************/ |
| 425 | unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) |
| 426 | { |
| 427 | return CORES_PER_CLUSTER; |
| 428 | } |
| 429 | |
| 430 | |
| 431 | void soc_early_platform_setup2(void) |
| 432 | { |
| 433 | dcfg_init(&dcfg_init_data); |
| 434 | /* |
| 435 | * Initialize system level generic timer for Socs |
| 436 | */ |
| 437 | delay_timer_init(NXP_TIMER_ADDR); |
| 438 | |
| 439 | #if LOG_LEVEL > 0 |
| 440 | /* Initialize the console to provide early debug support */ |
| 441 | plat_console_init(NXP_CONSOLE_ADDR, |
| 442 | NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); |
| 443 | #endif |
| 444 | } |
| 445 | |
| 446 | void soc_platform_setup(void) |
| 447 | { |
| 448 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 449 | static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; |
| 450 | static interrupt_prop_t ls_interrupt_props[] = { |
| 451 | PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), |
| 452 | PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) |
| 453 | }; |
| 454 | |
| 455 | plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, |
| 456 | PLATFORM_CORE_COUNT, |
| 457 | ls_interrupt_props, |
| 458 | ARRAY_SIZE(ls_interrupt_props), |
| 459 | target_mask_array, |
| 460 | plat_core_pos); |
| 461 | |
| 462 | plat_ls_gic_init(); |
| 463 | enable_init_timer(); |
| 464 | #ifdef LS_SYS_TIMCTL_BASE |
| 465 | ls_configure_sys_timer(LS_SYS_TIMCTL_BASE, |
| 466 | LS_CONFIG_CNTACR, |
| 467 | PLAT_LS_NSTIMER_FRAME_ID); |
| 468 | #endif |
| 469 | } |
| 470 | |
| 471 | /******************************************************************************* |
| 472 | * This function initializes the soc from the BL31 module |
| 473 | ******************************************************************************/ |
| 474 | void soc_init(void) |
| 475 | { |
Jiafei Pan | b27ac80 | 2021-07-20 17:14:32 +0800 | [diff] [blame] | 476 | uint8_t num_clusters, cores_per_cluster; |
| 477 | |
| 478 | get_cluster_info(soc_list, ARRAY_SIZE(soc_list), |
| 479 | &num_clusters, &cores_per_cluster); |
| 480 | |
| 481 | /* low-level init of the soc */ |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 482 | soc_init_start(); |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 483 | _init_global_data(); |
Jiafei Pan | a54d2e7 | 2022-06-10 11:47:15 +0800 | [diff] [blame] | 484 | soc_init_percpu(); |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 485 | _initialize_psci(); |
| 486 | |
| 487 | if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) { |
| 488 | ERROR("Unrecognized CCN variant detected."); |
| 489 | ERROR("Only CCN-508 is supported\n"); |
| 490 | panic(); |
| 491 | } |
| 492 | |
Pankaj Gupta | f24e1a3 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 493 | if (num_clusters == 6U) { |
| 494 | ccn_init(&plat_six_cluster_ccn_desc); |
| 495 | } else { |
| 496 | ccn_init(&plat_ccn_desc); |
| 497 | } |
| 498 | |
| 499 | plat_ls_interconnect_enter_coherency(num_clusters); |
| 500 | |
| 501 | /* Set platform security policies */ |
| 502 | _set_platform_security(); |
| 503 | |
| 504 | /* make sure any parallel init tasks are finished */ |
| 505 | soc_init_finish(); |
| 506 | |
| 507 | /* Initialize the crypto accelerator if enabled */ |
| 508 | if (is_sec_enabled() == false) { |
| 509 | INFO("SEC is disabled.\n"); |
| 510 | } else { |
| 511 | sec_init(NXP_CAAM_ADDR); |
| 512 | } |
| 513 | |
| 514 | } |
| 515 | |
| 516 | #ifdef NXP_WDOG_RESTART |
| 517 | static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, |
| 518 | void *handle, void *cookie) |
| 519 | { |
| 520 | uint8_t data = WDOG_RESET_FLAG; |
| 521 | |
| 522 | wr_nv_app_data(WDT_RESET_FLAG_OFFSET, |
| 523 | (uint8_t *)&data, sizeof(data)); |
| 524 | |
| 525 | mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | #endif |
| 530 | |
| 531 | void soc_runtime_setup(void) |
| 532 | { |
| 533 | |
| 534 | #ifdef NXP_WDOG_RESTART |
| 535 | request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); |
| 536 | #endif |
| 537 | } |
| 538 | #endif |