Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 7 | #include <mmio.h> |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 8 | #include <platform.h> |
| 9 | #include <platform_def.h> |
| 10 | #include <sunxi_def.h> |
| 11 | #include <xlat_tables_v2.h> |
| 12 | |
Andre Przywara | b5e29e2 | 2018-06-22 00:32:18 +0100 | [diff] [blame] | 13 | #include "sunxi_private.h" |
| 14 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 15 | static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 16 | MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, |
| 17 | MT_MEMORY | MT_RW | MT_SECURE), |
| 18 | MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, |
| 19 | MT_DEVICE | MT_RW | MT_SECURE), |
Andre Przywara | b3fddff | 2018-09-20 21:13:55 +0100 | [diff] [blame^] | 20 | MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, |
| 21 | MT_MEMORY | MT_RW | MT_SECURE), |
| 22 | MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, |
| 23 | SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, |
| 24 | SUNXI_DRAM_MAP_SIZE, |
| 25 | MT_MEMORY | MT_RO | MT_NS), |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 26 | {}, |
| 27 | }; |
| 28 | |
| 29 | unsigned int plat_get_syscnt_freq2(void) |
| 30 | { |
| 31 | return SUNXI_OSC24M_CLK_IN_HZ; |
| 32 | } |
| 33 | |
| 34 | uintptr_t plat_get_ns_image_entrypoint(void) |
| 35 | { |
| 36 | #ifdef PRELOADED_BL33_BASE |
| 37 | return PRELOADED_BL33_BASE; |
| 38 | #else |
| 39 | return PLAT_SUNXI_NS_IMAGE_OFFSET; |
| 40 | #endif |
| 41 | } |
| 42 | |
| 43 | void sunxi_configure_mmu_el3(int flags) |
| 44 | { |
| 45 | mmap_add_region(BL31_BASE, BL31_BASE, |
| 46 | BL31_LIMIT - BL31_BASE, |
| 47 | MT_MEMORY | MT_RW | MT_SECURE); |
| 48 | mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, |
| 49 | BL_CODE_END - BL_CODE_BASE, |
| 50 | MT_CODE | MT_SECURE); |
| 51 | mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, |
| 52 | BL_RO_DATA_END - BL_RO_DATA_BASE, |
| 53 | MT_RO_DATA | MT_SECURE); |
| 54 | mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, |
| 55 | BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
| 56 | MT_DEVICE | MT_RW | MT_SECURE); |
| 57 | mmap_add(sunxi_mmap); |
| 58 | init_xlat_tables(); |
| 59 | |
| 60 | enable_mmu_el3(0); |
| 61 | } |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 62 | |
| 63 | #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) |
| 64 | uint16_t sunxi_read_soc_id(void) |
| 65 | { |
| 66 | uint32_t reg = mmio_read_32(SRAM_VER_REG); |
| 67 | |
| 68 | /* Set bit 15 to prepare for the SOCID read. */ |
| 69 | mmio_write_32(SRAM_VER_REG, reg | BIT(15)); |
| 70 | |
| 71 | reg = mmio_read_32(SRAM_VER_REG); |
| 72 | |
| 73 | /* deactivate the SOCID access again */ |
| 74 | mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); |
| 75 | |
| 76 | return reg >> 16; |
| 77 | } |