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git01.mediatek.com / filogic / atf / 5735322d4af8182e60dfe57c74c40eb825287c75 / . / include / lib / cpus / aarch64 / cortex_a78.h
blob: caa512046cebb77db180a5933356e7996fff8138 [file] [log] [blame]
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]1/*
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]7#ifndef CORTEX_A78_H
8#define CORTEX_A78_H
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]9
10#include <lib/utils_def.h>
11
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]12#define CORTEX_A78_MIDR U(0x410FD410)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]13
14/*******************************************************************************
15 * CPU Extended Control register specific definitions.
16 ******************************************************************************/
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]17#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]18#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]23#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]24#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
Louis Mayencourtf57f1082019-05-14 11:00:45 +0100[diff] [blame]25
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]26/*******************************************************************************
27 * CPU Auxiliary Control register specific definitions.
28 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]29#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]30
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]31#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
32#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600[diff] [blame]33
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]34/*******************************************************************************
35 * CPU Activity Monitor Unit register specific definitions.
36 ******************************************************************************/
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]37#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
38#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
39#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
40#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]41
johpow019131eb82020-10-06 17:55:25 -0500[diff] [blame]42#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
43#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
Balint Dobszaydb2ec852019-07-15 11:46:20 +0200[diff] [blame]44
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500[diff] [blame]45#endif /* CORTEX_A78_H */