blob: cfe8c2a473c16bcc862ac6565514a94c134bb050 [file] [log] [blame]
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <mmio.h>
8#include <smmu_v3.h>
9
10/* Test for pending invalidate */
11#define INVAL_PENDING(base) \
12 smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK
13
14static inline uint32_t smmuv3_read_s_idr1(uintptr_t base)
15{
16 return mmio_read_32(base + SMMU_S_IDR1);
17}
18
19static inline uint32_t smmuv3_read_s_init(uintptr_t base)
20{
21 return mmio_read_32(base + SMMU_S_INIT);
22}
23
24static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value)
25{
26 mmio_write_32(base + SMMU_S_INIT, value);
27}
28
29/*
30 * Initialize the SMMU by invalidating all secure caches and TLBs.
31 *
32 * Returns 0 on success, and -1 on failure.
33 */
34int smmuv3_init(uintptr_t smmu_base)
35{
36 uint32_t idr1_reg;
37
38 /*
39 * Invalidation of secure caches and TLBs is required only if the SMMU
40 * supports secure state. If not, it's implementation defined as to how
41 * SMMU_S_INIT register is accessed.
42 */
43 idr1_reg = smmuv3_read_s_idr1(smmu_base);
44 if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
45 SMMU_S_IDR1_SECURE_IMPL_MASK)) {
46 return -1;
47 }
48
49 /* Initiate invalidation, and wait for it to finish */
50 smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
51 while (INVAL_PENDING(smmu_base))
52 ;
53
54 return 0;
55}