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Soby Mathew4b435f32016-09-14 15:51:44 +01001/*
Alexei Fedorovcb8fef62021-04-12 12:49:54 +01002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Soby Mathew4b435f32016-09-14 15:51:44 +01003 *
Achin Gupta69387312016-09-26 10:22:56 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew4b435f32016-09-14 15:51:44 +01005 */
6
Alexei Fedorov4348f492020-05-13 21:13:57 +01007/* Configuration: max 4 clusters with up to 4 CPUs */
8
Soby Mathew4b435f32016-09-14 15:51:44 +01009/dts-v1/;
10
Alexei Fedorov4348f492020-05-13 21:13:57 +010011#define AFF
12#define REG_32
13
14#include "fvp-defs.dtsi"
Alexei Fedorovcb8fef62021-04-12 12:49:54 +010015#include <dt-bindings/interrupt-controller/arm-gic.h>
Alexei Fedorov4348f492020-05-13 21:13:57 +010016
Soby Mathew4b435f32016-09-14 15:51:44 +010017/memreserve/ 0x80000000 0x00010000;
18
19/ {
20};
21
22/ {
23 model = "FVP Base";
24 compatible = "arm,vfp-base", "arm,vexpress";
25 interrupt-parent = <&gic>;
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 chosen { };
30
31 aliases {
32 serial0 = &v2m_serial0;
33 serial1 = &v2m_serial1;
34 serial2 = &v2m_serial2;
35 serial3 = &v2m_serial3;
36 };
37
38 psci {
39 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
40 method = "smc";
41 cpu_suspend = <0x84000001>;
42 cpu_off = <0x84000002>;
43 cpu_on = <0x84000003>;
44 sys_poweroff = <0x84000008>;
45 sys_reset = <0x84000009>;
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -060046 max-pwr-lvl = <2>;
Soby Mathew4b435f32016-09-14 15:51:44 +010047 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
Alexei Fedorov4348f492020-05-13 21:13:57 +010053 CPU_MAP
Soby Mathew4b435f32016-09-14 15:51:44 +010054
55 idle-states {
56 entry-method = "arm,psci";
57
58 CPU_SLEEP_0: cpu-sleep-0 {
59 compatible = "arm,idle-state";
60 local-timer-stop;
61 arm,psci-suspend-param = <0x0010000>;
62 entry-latency-us = <40>;
63 exit-latency-us = <100>;
64 min-residency-us = <150>;
65 };
66
67 CLUSTER_SLEEP_0: cluster-sleep-0 {
68 compatible = "arm,idle-state";
69 local-timer-stop;
70 arm,psci-suspend-param = <0x1010000>;
71 entry-latency-us = <500>;
72 exit-latency-us = <1000>;
73 min-residency-us = <2500>;
74 };
75 };
76
Alexei Fedorov4348f492020-05-13 21:13:57 +010077 CPUS
Soby Mathew4b435f32016-09-14 15:51:44 +010078
79 L2_0: l2-cache0 {
80 compatible = "cache";
81 };
82 };
83
84 memory@80000000 {
85 device_type = "memory";
86 reg = <0x00000000 0x80000000 0 0x7F000000>,
87 <0x00000008 0x80000000 0 0x80000000>;
88 };
89
90 gic: interrupt-controller@2f000000 {
91 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
94 interrupt-controller;
95 reg = <0x0 0x2f000000 0 0x10000>,
96 <0x0 0x2c000000 0 0x2000>,
97 <0x0 0x2c010000 0 0x2000>,
98 <0x0 0x2c02F000 0 0x2000>;
99 interrupts = <1 9 0xf04>;
100 };
101
102 timer {
103 compatible = "arm,armv8-timer";
Alexei Fedorovcb8fef62021-04-12 12:49:54 +0100104 interrupts = <GIC_PPI 13
105 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 14
107 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
108 <GIC_PPI 11
109 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
110 <GIC_PPI 10
111 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
Soby Mathew4b435f32016-09-14 15:51:44 +0100112 clock-frequency = <100000000>;
113 };
114
115 timer@2a810000 {
116 compatible = "arm,armv7-timer-mem";
117 reg = <0x0 0x2a810000 0x0 0x10000>;
118 clock-frequency = <100000000>;
119 #address-cells = <2>;
120 #size-cells = <2>;
121 ranges;
122 frame@2a830000 {
123 frame-number = <1>;
124 interrupts = <0 26 4>;
125 reg = <0x0 0x2a830000 0x0 0x10000>;
126 };
127 };
128
129 pmu {
130 compatible = "arm,armv8-pmuv3";
131 interrupts = <0 60 4>,
132 <0 61 4>,
133 <0 62 4>,
134 <0 63 4>;
135 };
136
137 smb {
138 compatible = "simple-bus";
139
140 #address-cells = <2>;
141 #size-cells = <1>;
142 ranges = <0 0 0 0x08000000 0x04000000>,
143 <1 0 0 0x14000000 0x04000000>,
144 <2 0 0 0x18000000 0x04000000>,
145 <3 0 0 0x1c000000 0x04000000>,
146 <4 0 0 0x0c000000 0x04000000>,
147 <5 0 0 0x10000000 0x04000000>;
148
149 #interrupt-cells = <1>;
150 interrupt-map-mask = <0 0 63>;
151 interrupt-map = <0 0 0 &gic 0 0 4>,
152 <0 0 1 &gic 0 1 4>,
153 <0 0 2 &gic 0 2 4>,
154 <0 0 3 &gic 0 3 4>,
155 <0 0 4 &gic 0 4 4>,
156 <0 0 5 &gic 0 5 4>,
157 <0 0 6 &gic 0 6 4>,
158 <0 0 7 &gic 0 7 4>,
159 <0 0 8 &gic 0 8 4>,
160 <0 0 9 &gic 0 9 4>,
161 <0 0 10 &gic 0 10 4>,
162 <0 0 11 &gic 0 11 4>,
163 <0 0 12 &gic 0 12 4>,
164 <0 0 13 &gic 0 13 4>,
165 <0 0 14 &gic 0 14 4>,
166 <0 0 15 &gic 0 15 4>,
167 <0 0 16 &gic 0 16 4>,
168 <0 0 17 &gic 0 17 4>,
169 <0 0 18 &gic 0 18 4>,
170 <0 0 19 &gic 0 19 4>,
171 <0 0 20 &gic 0 20 4>,
172 <0 0 21 &gic 0 21 4>,
173 <0 0 22 &gic 0 22 4>,
174 <0 0 23 &gic 0 23 4>,
175 <0 0 24 &gic 0 24 4>,
176 <0 0 25 &gic 0 25 4>,
177 <0 0 26 &gic 0 26 4>,
178 <0 0 27 &gic 0 27 4>,
179 <0 0 28 &gic 0 28 4>,
180 <0 0 29 &gic 0 29 4>,
181 <0 0 30 &gic 0 30 4>,
182 <0 0 31 &gic 0 31 4>,
183 <0 0 32 &gic 0 32 4>,
184 <0 0 33 &gic 0 33 4>,
185 <0 0 34 &gic 0 34 4>,
186 <0 0 35 &gic 0 35 4>,
187 <0 0 36 &gic 0 36 4>,
188 <0 0 37 &gic 0 37 4>,
189 <0 0 38 &gic 0 38 4>,
190 <0 0 39 &gic 0 39 4>,
191 <0 0 40 &gic 0 40 4>,
192 <0 0 41 &gic 0 41 4>,
193 <0 0 42 &gic 0 42 4>;
194
Balint Dobszay5ce2c322020-01-10 17:16:27 +0100195 #include "rtsm_ve-motherboard-aarch32.dtsi"
Soby Mathew4b435f32016-09-14 15:51:44 +0100196 };
197
198 panels {
199 panel@0 {
200 compatible = "panel";
201 mode = "XVGA";
202 refresh = <60>;
203 xres = <1024>;
204 yres = <768>;
205 pixclock = <15748>;
206 left_margin = <152>;
207 right_margin = <48>;
208 upper_margin = <23>;
209 lower_margin = <3>;
210 hsync_len = <104>;
211 vsync_len = <4>;
212 sync = <0>;
213 vmode = "FB_VMODE_NONINTERLACED";
214 tim2 = "TIM2_BCD", "TIM2_IPC";
215 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
216 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
217 bpp = <16>;
218 };
219 };
220};