Alexandre Torgue | deccca2 | 2020-10-07 15:29:52 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) 2023, STMicroelectronics - All Rights Reserved |
| 4 | * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | |
| 7 | #include <dt-bindings/clock/stm32mp25-clks.h> |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/reset/stm32mp25-resets.h> |
| 10 | |
| 11 | / { |
| 12 | #address-cells = <2>; |
| 13 | #size-cells = <2>; |
| 14 | |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu0: cpu@0 { |
| 20 | compatible = "arm,cortex-a35"; |
| 21 | device_type = "cpu"; |
| 22 | reg = <0>; |
| 23 | enable-method = "psci"; |
| 24 | }; |
| 25 | }; |
| 26 | |
| 27 | clocks { |
| 28 | clk_hse: clk-hse { |
| 29 | #clock-cells = <0>; |
| 30 | compatible = "fixed-clock"; |
| 31 | clock-frequency = <48000000>; |
| 32 | }; |
| 33 | |
| 34 | clk_hsi: clk-hsi { |
| 35 | #clock-cells = <0>; |
| 36 | compatible = "fixed-clock"; |
| 37 | clock-frequency = <64000000>; |
| 38 | }; |
| 39 | |
| 40 | clk_lse: clk-lse { |
| 41 | #clock-cells = <0>; |
| 42 | compatible = "fixed-clock"; |
| 43 | clock-frequency = <32768>; |
| 44 | }; |
| 45 | |
| 46 | clk_lsi: clk-lsi { |
| 47 | #clock-cells = <0>; |
| 48 | compatible = "fixed-clock"; |
| 49 | clock-frequency = <32000>; |
| 50 | }; |
| 51 | |
| 52 | clk_msi: clk-msi { |
| 53 | #clock-cells = <0>; |
| 54 | compatible = "fixed-clock"; |
| 55 | clock-frequency = <16000000>; |
| 56 | }; |
| 57 | }; |
| 58 | |
| 59 | intc: interrupt-controller@4ac00000 { |
| 60 | compatible = "arm,cortex-a7-gic"; |
| 61 | #interrupt-cells = <3>; |
| 62 | #address-cells = <1>; |
| 63 | interrupt-controller; |
| 64 | reg = <0x0 0x4ac10000 0x0 0x1000>, |
| 65 | <0x0 0x4ac20000 0x0 0x2000>, |
| 66 | <0x0 0x4ac40000 0x0 0x2000>, |
| 67 | <0x0 0x4ac60000 0x0 0x2000>; |
| 68 | }; |
| 69 | |
| 70 | timer: timer { |
| 71 | compatible = "arm,armv8-timer"; |
| 72 | interrupt-parent = <&intc>; |
| 73 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 74 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 75 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 76 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 77 | always-on; |
| 78 | }; |
| 79 | |
| 80 | soc@0 { |
| 81 | compatible = "simple-bus"; |
| 82 | #address-cells = <1>; |
| 83 | #size-cells = <1>; |
| 84 | interrupt-parent = <&intc>; |
| 85 | ranges = <0x0 0x0 0x0 0x80000000>; |
| 86 | |
| 87 | rifsc: rifsc@42080000 { |
| 88 | compatible = "st,stm32mp25-rifsc"; |
| 89 | reg = <0x42080000 0x1000>; |
| 90 | #address-cells = <1>; |
| 91 | #size-cells = <1>; |
| 92 | |
| 93 | usart2: serial@400e0000 { |
| 94 | compatible = "st,stm32h7-uart"; |
| 95 | reg = <0x400e0000 0x400>; |
| 96 | clocks = <&rcc CK_KER_USART2>; |
| 97 | resets = <&rcc USART2_R>; |
| 98 | status = "disabled"; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | rcc: rcc@44200000 { |
| 103 | compatible = "st,stm32mp25-rcc"; |
| 104 | reg = <0x44200000 0x10000>; |
| 105 | #clock-cells = <1>; |
| 106 | #reset-cells = <1>; |
| 107 | }; |
| 108 | |
| 109 | pwr: pwr@44210000 { |
| 110 | compatible = "st,stm32mp25-pwr"; |
| 111 | reg = <0x44210000 0x400>; |
| 112 | |
| 113 | vddio1: vddio1 { |
| 114 | regulator-name = "vddio1"; |
| 115 | }; |
| 116 | |
| 117 | vddio2: vddio2 { |
| 118 | regulator-name = "vddio2"; |
| 119 | }; |
| 120 | |
| 121 | vddio3: vddio3 { |
| 122 | regulator-name = "vddio3"; |
| 123 | }; |
| 124 | |
| 125 | vddio4: vddio4 { |
| 126 | regulator-name = "vddio4"; |
| 127 | }; |
| 128 | |
| 129 | vddio: vddio { |
| 130 | regulator-name = "vddio"; |
| 131 | }; |
| 132 | }; |
| 133 | |
| 134 | syscfg: syscon@44230000 { |
| 135 | compatible = "st,stm32mp25-syscfg", "syscon"; |
| 136 | reg = <0x44230000 0x10000>; |
| 137 | }; |
| 138 | |
| 139 | pinctrl: pinctrl@44240000 { |
| 140 | #address-cells = <1>; |
| 141 | #size-cells = <1>; |
| 142 | compatible = "st,stm32mp257-pinctrl"; |
| 143 | ranges = <0 0x44240000 0xa0400>; |
| 144 | pins-are-numbered; |
| 145 | |
| 146 | gpioa: gpio@44240000 { |
| 147 | gpio-controller; |
| 148 | #gpio-cells = <2>; |
| 149 | interrupt-controller; |
| 150 | #interrupt-cells = <2>; |
| 151 | reg = <0x0 0x400>; |
| 152 | clocks = <&rcc CK_BUS_GPIOA>; |
| 153 | st,bank-name = "GPIOA"; |
| 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
| 157 | gpiob: gpio@44250000 { |
| 158 | gpio-controller; |
| 159 | #gpio-cells = <2>; |
| 160 | interrupt-controller; |
| 161 | #interrupt-cells = <2>; |
| 162 | reg = <0x10000 0x400>; |
| 163 | clocks = <&rcc CK_BUS_GPIOB>; |
| 164 | st,bank-name = "GPIOB"; |
| 165 | status = "disabled"; |
| 166 | }; |
| 167 | |
| 168 | gpioc: gpio@44260000 { |
| 169 | gpio-controller; |
| 170 | #gpio-cells = <2>; |
| 171 | interrupt-controller; |
| 172 | #interrupt-cells = <2>; |
| 173 | reg = <0x20000 0x400>; |
| 174 | clocks = <&rcc CK_BUS_GPIOC>; |
| 175 | st,bank-name = "GPIOC"; |
| 176 | status = "disabled"; |
| 177 | }; |
| 178 | |
| 179 | gpiod: gpio@44270000 { |
| 180 | gpio-controller; |
| 181 | #gpio-cells = <2>; |
| 182 | interrupt-controller; |
| 183 | #interrupt-cells = <2>; |
| 184 | reg = <0x30000 0x400>; |
| 185 | clocks = <&rcc CK_BUS_GPIOD>; |
| 186 | st,bank-name = "GPIOD"; |
| 187 | status = "disabled"; |
| 188 | }; |
| 189 | |
| 190 | gpioe: gpio@44280000 { |
| 191 | gpio-controller; |
| 192 | #gpio-cells = <2>; |
| 193 | interrupt-controller; |
| 194 | #interrupt-cells = <2>; |
| 195 | reg = <0x40000 0x400>; |
| 196 | clocks = <&rcc CK_BUS_GPIOE>; |
| 197 | st,bank-name = "GPIOE"; |
| 198 | status = "disabled"; |
| 199 | }; |
| 200 | |
| 201 | gpiof: gpio@44290000 { |
| 202 | gpio-controller; |
| 203 | #gpio-cells = <2>; |
| 204 | interrupt-controller; |
| 205 | #interrupt-cells = <2>; |
| 206 | reg = <0x50000 0x400>; |
| 207 | clocks = <&rcc CK_BUS_GPIOF>; |
| 208 | st,bank-name = "GPIOF"; |
| 209 | status = "disabled"; |
| 210 | }; |
| 211 | |
| 212 | gpiog: gpio@442a0000 { |
| 213 | gpio-controller; |
| 214 | #gpio-cells = <2>; |
| 215 | interrupt-controller; |
| 216 | #interrupt-cells = <2>; |
| 217 | reg = <0x60000 0x400>; |
| 218 | clocks = <&rcc CK_BUS_GPIOG>; |
| 219 | st,bank-name = "GPIOG"; |
| 220 | status = "disabled"; |
| 221 | }; |
| 222 | |
| 223 | gpioh: gpio@442b0000 { |
| 224 | gpio-controller; |
| 225 | #gpio-cells = <2>; |
| 226 | interrupt-controller; |
| 227 | #interrupt-cells = <2>; |
| 228 | reg = <0x70000 0x400>; |
| 229 | clocks = <&rcc CK_BUS_GPIOH>; |
| 230 | st,bank-name = "GPIOH"; |
| 231 | status = "disabled"; |
| 232 | }; |
| 233 | |
| 234 | gpioi: gpio@442c0000 { |
| 235 | gpio-controller; |
| 236 | #gpio-cells = <2>; |
| 237 | interrupt-controller; |
| 238 | #interrupt-cells = <2>; |
| 239 | reg = <0x80000 0x400>; |
| 240 | clocks = <&rcc CK_BUS_GPIOI>; |
| 241 | st,bank-name = "GPIOI"; |
| 242 | status = "disabled"; |
| 243 | }; |
| 244 | |
| 245 | gpioj: gpio@442d0000 { |
| 246 | gpio-controller; |
| 247 | #gpio-cells = <2>; |
| 248 | interrupt-controller; |
| 249 | #interrupt-cells = <2>; |
| 250 | reg = <0x90000 0x400>; |
| 251 | clocks = <&rcc CK_BUS_GPIOJ>; |
| 252 | st,bank-name = "GPIOJ"; |
| 253 | status = "disabled"; |
| 254 | }; |
| 255 | |
| 256 | gpiok: gpio@442e0000 { |
| 257 | gpio-controller; |
| 258 | #gpio-cells = <2>; |
| 259 | interrupt-controller; |
| 260 | #interrupt-cells = <2>; |
| 261 | reg = <0xa0000 0x400>; |
| 262 | clocks = <&rcc CK_BUS_GPIOK>; |
| 263 | st,bank-name = "GPIOK"; |
| 264 | status = "disabled"; |
| 265 | }; |
| 266 | }; |
| 267 | |
| 268 | pinctrl_z: pinctrl@46200000 { |
| 269 | #address-cells = <1>; |
| 270 | #size-cells = <1>; |
| 271 | compatible = "st,stm32mp257-z-pinctrl"; |
| 272 | ranges = <0 0x46200000 0x400>; |
| 273 | pins-are-numbered; |
| 274 | |
| 275 | gpioz: gpio@46200000 { |
| 276 | gpio-controller; |
| 277 | #gpio-cells = <2>; |
| 278 | interrupt-controller; |
| 279 | #interrupt-cells = <2>; |
| 280 | reg = <0 0x400>; |
| 281 | clocks = <&rcc CK_BUS_GPIOZ>; |
| 282 | st,bank-name = "GPIOZ"; |
| 283 | st,bank-ioport = <11>; |
| 284 | status = "disabled"; |
| 285 | }; |
| 286 | |
| 287 | }; |
| 288 | }; |
| 289 | }; |