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Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Remi Pommareldb289172019-04-04 23:12:56 +02002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00009#include <common/debug.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000010#include <drivers/arm/gicv2.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +010011#include <drivers/console.h>
12#include <errno.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000013#include <lib/mmio.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +010014#include <lib/psci/psci.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000015#include <plat/common/platform.h>
16#include <platform_def.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000017
Carlo Caionee5a30db2019-08-24 17:31:51 +010018#include "aml_private.h"
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000019
20#define SCPI_POWER_ON 0
21#define SCPI_POWER_RETENTION 1
22#define SCPI_POWER_OFF 3
23
24#define SCPI_SYSTEM_SHUTDOWN 0
25#define SCPI_SYSTEM_REBOOT 1
26
Carlo Caione883e3ca2019-08-28 15:19:56 +010027static uintptr_t gxl_sec_entrypoint;
28static volatile uint32_t gxl_cpu0_go;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000029
Remi Pommareldb289172019-04-04 23:12:56 +020030static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000031{
Carlo Caione1afdfb02019-08-24 18:47:06 +010032 unsigned int core = plat_calc_core_pos(mpidr);
Carlo Caione883e3ca2019-08-28 15:19:56 +010033 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000034
35 mmio_write_64(cpu_mailbox_addr, value);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000036}
37
Remi Pommareldb289172019-04-04 23:12:56 +020038static void gxl_pm_reset(u_register_t mpidr)
39{
Carlo Caione1afdfb02019-08-24 18:47:06 +010040 unsigned int core = plat_calc_core_pos(mpidr);
Carlo Caione883e3ca2019-08-28 15:19:56 +010041 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8;
Remi Pommareldb289172019-04-04 23:12:56 +020042
43 mmio_write_32(cpu_mailbox_addr, 0);
44}
45
Carlo Caione883e3ca2019-08-28 15:19:56 +010046static void __dead2 gxl_system_reset(void)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000047{
48 INFO("BL31: PSCI_SYSTEM_RESET\n");
49
Remi Pommareldb289172019-04-04 23:12:56 +020050 u_register_t mpidr = read_mpidr_el1();
Carlo Caione883e3ca2019-08-28 15:19:56 +010051 uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3);
Remi Pommareldb289172019-04-04 23:12:56 +020052 int ret;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000053
54 NOTICE("BL31: Reboot reason: 0x%x\n", status);
55
56 status &= 0xFFFF0FF0;
57
58 console_flush();
59
Carlo Caione883e3ca2019-08-28 15:19:56 +010060 mmio_write_32(AML_AO_RTI_STATUS_REG3, status);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000061
Carlo Caione7bb83022019-08-28 10:08:24 +010062 ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000063
64 if (ret != 0) {
Remi Pommareldb289172019-04-04 23:12:56 +020065 ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000066 panic();
67 }
68
Remi Pommareldb289172019-04-04 23:12:56 +020069 gxl_pm_reset(mpidr);
70
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000071 wfi();
72
73 ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
74 panic();
75}
76
Carlo Caione883e3ca2019-08-28 15:19:56 +010077static void __dead2 gxl_system_off(void)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000078{
79 INFO("BL31: PSCI_SYSTEM_OFF\n");
80
Remi Pommareldb289172019-04-04 23:12:56 +020081 u_register_t mpidr = read_mpidr_el1();
82 int ret;
83
Carlo Caione7bb83022019-08-28 10:08:24 +010084 ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000085
86 if (ret != 0) {
Remi Pommareldb289172019-04-04 23:12:56 +020087 ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000088 panic();
89 }
90
Remi Pommareldb289172019-04-04 23:12:56 +020091 gxl_pm_set_reset_addr(mpidr, 0);
92 gxl_pm_reset(mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000093
94 wfi();
95
96 ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
97 panic();
98}
99
Carlo Caione883e3ca2019-08-28 15:19:56 +0100100static int32_t gxl_pwr_domain_on(u_register_t mpidr)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000101{
Carlo Caione1afdfb02019-08-24 18:47:06 +0100102 unsigned int core = plat_calc_core_pos(mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000103
104 /* CPU0 can't be turned OFF, emulate it with a WFE loop */
Carlo Caione1afdfb02019-08-24 18:47:06 +0100105 if (core == AML_PRIMARY_CPU) {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000106 VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
107
Carlo Caione883e3ca2019-08-28 15:19:56 +0100108 gxl_cpu0_go = 1;
109 flush_dcache_range((uintptr_t)&gxl_cpu0_go,
110 sizeof(gxl_cpu0_go));
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000111 dsb();
112 isb();
113
114 sev();
115
116 return PSCI_E_SUCCESS;
117 }
118
Carlo Caione883e3ca2019-08-28 15:19:56 +0100119 gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint);
Carlo Caione7bb83022019-08-28 10:08:24 +0100120 aml_scpi_set_css_power_state(mpidr,
121 SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000122 dmbsy();
123 sev();
124
125 return PSCI_E_SUCCESS;
126}
127
Carlo Caione883e3ca2019-08-28 15:19:56 +0100128static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000129{
Carlo Caione1afdfb02019-08-24 18:47:06 +0100130 unsigned int core = plat_calc_core_pos(read_mpidr_el1());
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000131
132 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
133 PLAT_LOCAL_STATE_OFF);
134
Carlo Caione1afdfb02019-08-24 18:47:06 +0100135 if (core == AML_PRIMARY_CPU) {
Carlo Caione883e3ca2019-08-28 15:19:56 +0100136 gxl_cpu0_go = 0;
137 flush_dcache_range((uintptr_t)&gxl_cpu0_go,
138 sizeof(gxl_cpu0_go));
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000139 dsb();
140 isb();
141 }
142
143 gicv2_pcpu_distif_init();
144 gicv2_cpuif_enable();
145}
146
Carlo Caione883e3ca2019-08-28 15:19:56 +0100147static void gxl_pwr_domain_off(const psci_power_state_t *target_state)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000148{
149 u_register_t mpidr = read_mpidr_el1();
Carlo Caione1afdfb02019-08-24 18:47:06 +0100150 unsigned int core = plat_calc_core_pos(mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000151
152 gicv2_cpuif_disable();
153
154 /* CPU0 can't be turned OFF, emulate it with a WFE loop */
Carlo Caione1afdfb02019-08-24 18:47:06 +0100155 if (core == AML_PRIMARY_CPU)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000156 return;
157
Carlo Caione7bb83022019-08-28 10:08:24 +0100158 aml_scpi_set_css_power_state(mpidr,
159 SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000160}
161
Carlo Caione883e3ca2019-08-28 15:19:56 +0100162static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000163 *target_state)
164{
Remi Pommarel3d50b432019-07-30 18:04:38 +0200165 u_register_t mpidr = read_mpidr_el1();
Carlo Caione1afdfb02019-08-24 18:47:06 +0100166 unsigned int core = plat_calc_core_pos(mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000167
168 /* CPU0 can't be turned OFF, emulate it with a WFE loop */
Carlo Caione1afdfb02019-08-24 18:47:06 +0100169 if (core == AML_PRIMARY_CPU) {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000170 VERBOSE("BL31: CPU0 entering wait loop...\n");
171
Carlo Caione883e3ca2019-08-28 15:19:56 +0100172 while (gxl_cpu0_go == 0)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000173 wfe();
174
175 VERBOSE("BL31: CPU0 resumed.\n");
176
Remi Pommarel3d50b432019-07-30 18:04:38 +0200177 /*
178 * Because setting CPU0's warm reset entrypoint through PSCI
179 * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
180 * to work, jump to it manually.
181 * In order to avoid an assert, mmu has to be disabled.
182 */
183 disable_mmu_el3();
Carlo Caione883e3ca2019-08-28 15:19:56 +0100184 ((void(*)(void))gxl_sec_entrypoint)();
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000185 }
186
187 dsbsy();
Remi Pommarel3d50b432019-07-30 18:04:38 +0200188 gxl_pm_set_reset_addr(mpidr, 0);
189 gxl_pm_reset(mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000190
191 for (;;)
192 wfi();
193}
194
195/*******************************************************************************
196 * Platform handlers and setup function.
197 ******************************************************************************/
Carlo Caione883e3ca2019-08-28 15:19:56 +0100198static const plat_psci_ops_t gxl_ops = {
199 .pwr_domain_on = gxl_pwr_domain_on,
200 .pwr_domain_on_finish = gxl_pwr_domain_on_finish,
201 .pwr_domain_off = gxl_pwr_domain_off,
202 .pwr_domain_pwr_down_wfi = gxl_pwr_domain_pwr_down_wfi,
203 .system_off = gxl_system_off,
204 .system_reset = gxl_system_reset,
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000205};
206
207int plat_setup_psci_ops(uintptr_t sec_entrypoint,
208 const plat_psci_ops_t **psci_ops)
209{
Carlo Caione883e3ca2019-08-28 15:19:56 +0100210 gxl_sec_entrypoint = sec_entrypoint;
211 *psci_ops = &gxl_ops;
212 gxl_cpu0_go = 0;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000213 return 0;
214}