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Dimitris Papastamose08005a2017-10-12 13:02:29 +01001/*
Boyan Karatotevb2953472024-11-06 14:55:35 +00002 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
Dimitris Papastamose08005a2017-10-12 13:02:29 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +01007#ifndef AMU_H
8#define AMU_H
Dimitris Papastamose08005a2017-10-12 13:02:29 +01009
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010010#include <stdbool.h>
Chris Kayf11909f2021-08-19 11:21:52 +010011#include <stdint.h>
12
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +010013#include <context.h>
Alexei Fedorov7e6306b2020-07-14 08:17:56 +010014
Chris Kayf11909f2021-08-19 11:21:52 +010015#include <platform_def.h>
16
Andre Przywara906776e2023-03-03 10:30:06 +000017#if ENABLE_FEAT_AMU
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +010018#if __aarch64__
Boyan Karatotev1e966f32023-03-27 17:02:43 +010019void amu_enable(cpu_context_t *ctx);
Boyan Karatotevb2953472024-11-06 14:55:35 +000020void amu_init_el3(unsigned int core_pos);
Boyan Karatotev1e966f32023-03-27 17:02:43 +010021void amu_init_el2_unused(void);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010022void amu_enable_per_world(per_world_context_t *per_world_ctx);
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +010023#else
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010024void amu_enable(bool el2_unused);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010025#endif /* __aarch64__ */
26
Andre Przywara906776e2023-03-03 10:30:06 +000027#else
28#if __aarch64__
Boyan Karatotev1e966f32023-03-27 17:02:43 +010029void amu_enable(cpu_context_t *ctx)
30{
31}
Boyan Karatotevb2953472024-11-06 14:55:35 +000032void amu_init_el3(unsigned int core_pos)
Boyan Karatotev1e966f32023-03-27 17:02:43 +010033{
34}
35void amu_init_el2_unused(void)
Andre Przywara906776e2023-03-03 10:30:06 +000036{
37}
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010038void amu_enable_per_world(per_world_context_t *per_world_ctx)
39{
40}
Andre Przywara906776e2023-03-03 10:30:06 +000041#else
42static inline void amu_enable(bool el2_unused)
43{
44}
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010045#endif /*__aarch64__ */
46#endif /* ENABLE_FEAT_AMU */
Dimitris Papastamose08005a2017-10-12 13:02:29 +010047
Chris Kayf11909f2021-08-19 11:21:52 +010048/*
Boyan Karatotevb2953472024-11-06 14:55:35 +000049 * Per-core list of the counters to be enabled. Value will be written into
50 * AMCNTENSET1_EL0 verbatim.
Chris Kayf11909f2021-08-19 11:21:52 +010051 */
Boyan Karatotevb2953472024-11-06 14:55:35 +000052#if ENABLE_AMU_AUXILIARY_COUNTERS
53extern uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT];
54#endif
Chris Kayf11909f2021-08-19 11:21:52 +010055
Boyan Karatotevb2953472024-11-06 14:55:35 +000056#define CTX_AMU_GRP0_ALL U(4)
57#define CTX_AMU_GRP1_ALL U(16)
Chris Kayf11909f2021-08-19 11:21:52 +010058
Boyan Karatotevb2953472024-11-06 14:55:35 +000059typedef struct amu_regs {
60 u_register_t grp0[CTX_AMU_GRP0_ALL];
61#if ENABLE_AMU_AUXILIARY_COUNTERS
62 u_register_t grp1[CTX_AMU_GRP1_ALL];
63#endif
64} amu_regs_t;
65
66static inline u_register_t read_amu_grp0_ctx_reg(amu_regs_t *ctx, size_t index)
67{
68 return ctx->grp0[index];
69}
70
71static inline void write_amu_grp0_ctx_reg(amu_regs_t *ctx, size_t index, u_register_t val)
72{
73 ctx->grp0[index] = val;
74}
75
76static inline uint16_t get_amu_aux_enables(size_t index)
77{
78#if ENABLE_AMU_AUXILIARY_COUNTERS
79 return plat_amu_aux_enables[index];
80#else
81 return 0;
82#endif
83}
84
85static inline u_register_t read_amu_grp1_ctx_reg(amu_regs_t *ctx, size_t index)
86{
87#if ENABLE_AMU_AUXILIARY_COUNTERS
88 return ctx->grp1[index];
89#else
90 return 0;
91#endif
92}
93
94static inline void write_amu_grp1_ctx_reg(amu_regs_t *ctx, size_t index, u_register_t val)
95{
96#if ENABLE_AMU_AUXILIARY_COUNTERS
97 ctx->grp1[index] = val;
98#endif
99}
Chris Kayf11909f2021-08-19 11:21:52 +0100100
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100101#endif /* AMU_H */