| Saurabh Gorecha | 70389ca | 2020-04-22 21:31:24 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef __PLAT_MACROS_S__ |
| 9 | #define __PLAT_MACROS_S__ |
| 10 | |
| 11 | #include <drivers/arm/gic_common.h> |
| 12 | #include <drivers/arm/gicv2.h> |
| 13 | #include <drivers/arm/gicv3.h> |
| 14 | |
| 15 | #include <platform_def.h> |
| 16 | |
| 17 | .section .rodata.gic_reg_name, "aS" |
| 18 | /* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ |
| 19 | gicc_regs: |
| 20 | .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" |
| 21 | |
| 22 | /* Applicable only to GICv3 with SRE enabled */ |
| 23 | icc_regs: |
| 24 | .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" |
| 25 | |
| 26 | /* Registers common to both GICv2 and GICv3 */ |
| 27 | gicd_pend_reg: |
| 28 | .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ |
| 29 | " Offset:\t\t\tvalue\n" |
| 30 | newline: |
| 31 | .asciz "\n" |
| 32 | spacer: |
| 33 | .asciz ":\t\t0x" |
| 34 | |
| 35 | /** Macro : plat_crash_print_regs |
| 36 | * This macro allows the crash reporting routine to print GIC registers |
| 37 | * in case of an unhandled exception in BL31. This aids in debugging and |
| 38 | * this macro can be defined to be empty in case GIC register reporting is |
| 39 | * not desired. |
| 40 | * The below required platform porting macro |
| 41 | * prints out relevant GIC registers whenever an |
| 42 | * unhandled exception is taken in BL31. |
| 43 | * Clobbers: x0 - x10, x26, x27, sp |
| 44 | * --------------------------------------------- |
| 45 | */ |
| 46 | .macro plat_crash_print_regs |
| 47 | print_gic_regs: |
| 48 | ldr x26, =QTI_GICD_BASE |
| 49 | ldr x27, =QTI_GICC_BASE |
| 50 | |
| 51 | /* Check for GICv3 system register access */ |
| 52 | mrs x7, id_aa64pfr0_el1 |
| 53 | ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH |
| 54 | cmp x7, #1 |
| 55 | b.ne print_gicv2 |
| 56 | |
| 57 | /* Check for SRE enable */ |
| 58 | mrs x8, ICC_SRE_EL3 |
| 59 | tst x8, #ICC_SRE_SRE_BIT |
| 60 | b.eq print_gicv2 |
| 61 | |
| 62 | /* Load the icc reg list to x6 */ |
| 63 | adr x6, icc_regs |
| 64 | /* Load the icc regs to gp regs used by str_in_crash_buf_print */ |
| 65 | mrs x8, ICC_HPPIR0_EL1 |
| 66 | mrs x9, ICC_HPPIR1_EL1 |
| 67 | mrs x10, ICC_CTLR_EL3 |
| 68 | /* Store to the crash buf and print to console */ |
| 69 | bl str_in_crash_buf_print |
| 70 | b print_gic_common |
| 71 | |
| 72 | print_gicv2: |
| 73 | /* Load the gicc reg list to x6 */ |
| 74 | adr x6, gicc_regs |
| 75 | /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ |
| 76 | ldr w8, [x27, #GICC_HPPIR] |
| 77 | ldr w9, [x27, #GICC_AHPPIR] |
| 78 | ldr w10, [x27, #GICC_CTLR] |
| 79 | /* Store to the crash buf and print to console */ |
| 80 | bl str_in_crash_buf_print |
| 81 | |
| 82 | print_gic_common: |
| 83 | /* Print the GICD_ISPENDR regs */ |
| 84 | add x7, x26, #GICD_ISPENDR |
| 85 | adr x4, gicd_pend_reg |
| 86 | bl asm_print_str |
| 87 | gicd_ispendr_loop: |
| 88 | sub x4, x7, x26 |
| 89 | cmp x4, #0x280 |
| 90 | b.eq exit_print_gic_regs |
| 91 | bl asm_print_hex |
| 92 | |
| 93 | adr x4, spacer |
| 94 | bl asm_print_str |
| 95 | |
| 96 | ldr x4, [x7], #8 |
| 97 | bl asm_print_hex |
| 98 | |
| 99 | adr x4, newline |
| 100 | bl asm_print_str |
| 101 | b gicd_ispendr_loop |
| 102 | exit_print_gic_regs: |
| 103 | |
| 104 | .endm |
| 105 | |
| 106 | #endif /* __PLAT_MACROS_S__ */ |