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git01.mediatek.com / filogic / atf / b27cc468202c43d66cf947d578da8d11166201b0 / . / fdts / stm32mp157c-odyssey-som.dtsi
blob: 091e327cf78fbdb12ee23819fd075896ee09f3da [file] [log] [blame]
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]1/*
2 * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
3 * Copyright (C) 2021, Grzegorz Szymaszek.
4 *
5 * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
6 */
7
8#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxac-pinctrl.dtsi"
12#include <dt-bindings/clock/stm32mp1-clksrc.h>
13#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
14
15/ {
16 memory@c0000000 {
17 device_type = "memory";
18 reg = <0xc0000000 0x20000000>;
19 };
20
21 vin: vin {
22 compatible = "regulator-fixed";
23 regulator-name = "vin";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 };
28};
29
30&bsec {
31 board_id: board_id@ec {
32 reg = <0xec 0x4>;
33 st,non-secure-otp;
34 };
35};
36
37&clk_hse {
38 st,digbypass;
39};
40
41&cpu0 {
42 cpu-supply = <&vddcore>;
43};
44
45&cpu1 {
46 cpu-supply = <&vddcore>;
47};
48
49&cryp1 {
50 status = "okay";
51};
52
53&hash1 {
54 status = "okay";
55};
56
57&i2c2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c2_pins_a>;
60 clock-frequency = <400000>;
61 i2c-scl-rising-time-ns = <185>;
62 i2c-scl-falling-time-ns = <20>;
63 status = "okay";
64
65 pmic: stpmic@33 {
66 compatible = "st,stpmic1";
67 reg = <0x33>;
68 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 status = "okay";
72
73 regulators {
74 compatible = "st,stpmic1-regulators";
75 buck1-supply = <&vin>;
76 buck2-supply = <&vin>;
77 buck3-supply = <&vin>;
78 buck4-supply = <&vin>;
79 ldo1-supply = <&v3v3>;
80 ldo2-supply = <&vin>;
81 ldo3-supply = <&vdd_ddr>;
82 ldo4-supply = <&vin>;
83 ldo5-supply = <&vin>;
84 ldo6-supply = <&v3v3>;
85 vref_ddr-supply = <&vin>;
86 boost-supply = <&vin>;
87 pwr_sw1-supply = <&bst_out>;
88 pwr_sw2-supply = <&bst_out>;
89
90 vddcore: buck1 {
91 regulator-name = "vddcore";
92 regulator-min-microvolt = <1200000>;
93 regulator-max-microvolt = <1350000>;
94 regulator-always-on;
95 regulator-initial-mode = <0>;
96 regulator-over-current-protection;
97 };
98
99 vdd_ddr: buck2 {
100 regulator-name = "vdd_ddr";
101 regulator-min-microvolt = <1350000>;
102 regulator-max-microvolt = <1350000>;
103 regulator-always-on;
104 regulator-initial-mode = <0>;
105 regulator-over-current-protection;
106 };
107
108 vdd: buck3 {
109 regulator-name = "vdd";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 regulator-always-on;
113 st,mask-reset;
114 regulator-initial-mode = <0>;
115 regulator-over-current-protection;
116 };
117
118 v3v3: buck4 {
119 regulator-name = "v3v3";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 regulator-always-on;
123 regulator-over-current-protection;
124 regulator-initial-mode = <0>;
125 };
126
127 v1v8_audio: ldo1 {
128 regulator-name = "v1v8_audio";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <1800000>;
131 regulator-always-on;
132 };
133
134 v3v3_hdmi: ldo2 {
135 regulator-name = "v3v3_hdmi";
136 regulator-min-microvolt = <3300000>;
137 regulator-max-microvolt = <3300000>;
138 regulator-always-on;
139 };
140
141 vtt_ddr: ldo3 {
142 regulator-name = "vtt_ddr";
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]143 regulator-always-on;
144 regulator-over-current-protection;
Ahmad Fatoum9d3c53c2022-06-02 06:28:31 +0200[diff] [blame]145 st,regulator-sink-source;
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]146 };
147
148 vdd_usb: ldo4 {
149 regulator-name = "vdd_usb";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
154
155 vdda: ldo5 {
156 regulator-name = "vdda";
157 regulator-min-microvolt = <2900000>;
158 regulator-max-microvolt = <2900000>;
159 regulator-boot-on;
160 };
161
162 v1v2_hdmi: ldo6 {
163 regulator-name = "v1v2_hdmi";
164 regulator-min-microvolt = <1200000>;
165 regulator-max-microvolt = <1200000>;
166 regulator-always-on;
167 };
168
169 vref_ddr: vref_ddr {
170 regulator-name = "vref_ddr";
171 regulator-always-on;
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]172 };
173
174 bst_out: boost {
175 regulator-name = "bst_out";
176 };
177
178 vbus_otg: pwr_sw1 {
179 regulator-name = "vbus_otg";
180 };
181
182 vbus_sw: pwr_sw2 {
183 regulator-name = "vbus_sw";
184 regulator-active-discharge = <1>;
185 };
186 };
187
188 pmic_watchdog: watchdog {
189 compatible = "st,stpmic1-wdt";
190 status = "disabled";
191 };
192 };
193};
194
195&iwdg2 {
196 timeout-sec = <32>;
197 status = "okay";
198};
199
200&pwr_regulators {
201 vdd-supply = <&vdd>;
202 vdd_3v3_usbfs-supply = <&vdd_usb>;
203};
204
205&rcc {
Grzegorz Szymaszek2366adc2021-04-21 19:46:18 +0200[diff] [blame]206 st,clksrc = <
207 CLK_MPU_PLL1P
208 CLK_AXI_PLL2P
209 CLK_MCU_PLL3P
210 CLK_PLL12_HSE
211 CLK_PLL3_HSE
212 CLK_PLL4_HSE
213 CLK_RTC_LSE
214 CLK_MCO1_DISABLED
215 CLK_MCO2_DISABLED
216 >;
217
218 st,clkdiv = <
219 1 /*MPU*/
220 0 /*AXI*/
221 0 /*MCU*/
222 1 /*APB1*/
223 1 /*APB2*/
224 1 /*APB3*/
225 1 /*APB4*/
226 2 /*APB5*/
227 23 /*RTC*/
228 0 /*MCO1*/
229 0 /*MCO2*/
230 >;
231
232 st,pkcs = <
233 CLK_CKPER_HSE
234 CLK_FMC_ACLK
235 CLK_QSPI_ACLK
236 CLK_ETH_PLL4P
237 CLK_SDMMC12_PLL4P
238 CLK_DSI_DSIPLL
239 CLK_STGEN_HSE
240 CLK_USBPHY_HSE
241 CLK_SPI2S1_PLL3Q
242 CLK_SPI2S23_PLL3Q
243 CLK_SPI45_HSI
244 CLK_SPI6_HSI
245 CLK_I2C46_HSI
246 CLK_SDMMC3_PLL4P
247 CLK_USBO_USBPHY
248 CLK_ADC_CKPER
249 CLK_CEC_LSE
250 CLK_I2C12_HSI
251 CLK_I2C35_HSI
252 CLK_UART1_HSI
253 CLK_UART24_HSI
254 CLK_UART35_HSI
255 CLK_UART6_HSI
256 CLK_UART78_HSI
257 CLK_SPDIF_PLL4P
258 CLK_FDCAN_PLL4R
259 CLK_SAI1_PLL3Q
260 CLK_SAI2_PLL3Q
261 CLK_SAI3_PLL3Q
262 CLK_SAI4_PLL3Q
263 CLK_RNG1_LSI
264 CLK_RNG2_LSI
265 CLK_LPTIM1_PCLK1
266 CLK_LPTIM23_PCLK3
267 CLK_LPTIM45_LSE
268 >;
269
270 /* VCO = 1300.0 MHz => P = 650 (CPU) */
271 pll1: st,pll@0 {
272 compatible = "st,stm32mp1-pll";
273 reg = <0>;
274 cfg = <2 80 0 0 0 PQR(1,0,0)>;
275 frac = <0x800>;
276 };
277
278 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
279 pll2: st,pll@1 {
280 compatible = "st,stm32mp1-pll";
281 reg = <1>;
282 cfg = <2 65 1 0 0 PQR(1,1,1)>;
283 frac = <0x1400>;
284 };
285
286 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
287 pll3: st,pll@2 {
288 compatible = "st,stm32mp1-pll";
289 reg = <2>;
290 cfg = <1 33 1 16 36 PQR(1,1,1)>;
291 frac = <0x1a04>;
292 };
293
294 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
295 pll4: st,pll@3 {
296 compatible = "st,stm32mp1-pll";
297 reg = <3>;
298 cfg = <3 98 5 7 7 PQR(1,1,1)>;
299 };
300};
301
302&rng1 {
303 status = "okay";
304};
305
306&rtc {
307 status = "okay";
308};
309
310&sdmmc2 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
313 non-removable;
314 no-sd;
315 no-sdio;
316 st,neg-edge;
317 bus-width = <8>;
318 vmmc-supply = <&v3v3>;
319 vqmmc-supply = <&vdd>;
320 mmc-ddr-3_3v;
321 status = "okay";
322};