blob: d919fa1d2ad299e943a434b8f346c6e3ec8a77c4 [file] [log] [blame]
Xing Zheng93280b72016-10-26 21:25:26 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Xing Zheng93280b72016-10-26 21:25:26 +08005 */
6
Xing Zheng93280b72016-10-26 21:25:26 +08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <arch_helpers.h>
10#include <common/debug.h>
11#include <drivers/delay_timer.h>
12#include <lib/mmio.h>
13
Xing Zheng93280b72016-10-26 21:25:26 +080014#include <m0_ctl.h>
15#include <plat_private.h>
16#include <rk3399_def.h>
Xing Zheng22a98712017-02-24 14:56:41 +080017#include <secure.h>
Xing Zheng93280b72016-10-26 21:25:26 +080018#include <soc.h>
19
20void m0_init(void)
21{
22 /* secure config for M0 */
23 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
Xing Zheng22a98712017-02-24 14:56:41 +080024 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
Xing Zheng93280b72016-10-26 21:25:26 +080025
Lin Huang8140b7d2016-12-30 13:53:25 +080026 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
27 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
Xing Zheng93280b72016-10-26 21:25:26 +080028
29 /*
30 * To switch the parent to xin24M and div == 1,
31 *
32 * We need to close most of the PLLs and clocks except the OSC 24MHz
33 * durning suspend, and this should be enough to supplies the ddrfreq,
34 * For the simple handle, we just keep the fixed 24MHz to supply the
35 * suspend and ddrfreq directly.
36 */
37 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
38 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
Lin Huangb4a76762016-12-12 15:18:08 +080039
40 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
Xing Zheng93280b72016-10-26 21:25:26 +080041}
42
Lin Huang00960ba2018-04-20 15:55:21 +080043void m0_configure_execute_addr(uintptr_t addr)
44{
45 /* set the execute address for M0 */
46 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
47 BITS_WITH_WMASK((addr >> 12) & 0xffff,
48 0xffff, 0));
49 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
50 BITS_WITH_WMASK((addr >> 28) & 0xf,
51 0xf, 0));
52}
53
Xing Zheng93280b72016-10-26 21:25:26 +080054void m0_start(void)
55{
Lin Huangb4a76762016-12-12 15:18:08 +080056 /* enable clocks for M0 */
57 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
58 BITS_WITH_WMASK(0x0, 0xf, 0));
59
Xing Zheng93280b72016-10-26 21:25:26 +080060 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */
61 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
Derek Basehorec8e5c782017-02-24 14:33:03 +080062 dmbst();
Xing Zheng93280b72016-10-26 21:25:26 +080063
Lin Huangb4a76762016-12-12 15:18:08 +080064 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
65 BITS_WITH_WMASK(0x0, 0x4, 0));
Xing Zheng93280b72016-10-26 21:25:26 +080066
Lin Huangb4a76762016-12-12 15:18:08 +080067 udelay(5);
Xing Zheng93280b72016-10-26 21:25:26 +080068 /* start M0 */
69 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
Lin Huangb4a76762016-12-12 15:18:08 +080070 BITS_WITH_WMASK(0x0, 0x20, 0));
71 dmbst();
Xing Zheng93280b72016-10-26 21:25:26 +080072}
73
74void m0_stop(void)
75{
76 /* stop M0 */
77 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
78 BITS_WITH_WMASK(0x24, 0x24, 0));
79
80 /* disable clocks for M0 */
81 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
Lin Huangb4a76762016-12-12 15:18:08 +080082 BITS_WITH_WMASK(0xf, 0xf, 0));
Xing Zheng93280b72016-10-26 21:25:26 +080083}
84
85void m0_wait_done(void)
86{
Lin Huangb4a76762016-12-12 15:18:08 +080087 do {
Derek Basehorec8e5c782017-02-24 14:33:03 +080088 /*
89 * Don't starve the M0 for access to SRAM, so delay before
90 * reading the PARAM_M0_DONE value again.
91 */
92 udelay(5);
Xing Zheng93280b72016-10-26 21:25:26 +080093 dsb();
Lin Huangb4a76762016-12-12 15:18:08 +080094 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
95
96 /*
97 * Let the M0 settle into WFI before we leave. This is so we don't reset
98 * the M0 in a bad spot which can cause problems with the M0.
99 */
100 udelay(10);
101 dsb();
Xing Zheng93280b72016-10-26 21:25:26 +0800102}