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git01.mediatek.com / filogic / atf / b26da3ca52d07798bd6028c4231df3eb563cef05 / . / plat / marvell / common / mss / mss_ipc_drv.h
blob: bcb4b2d8f9adbbe5179356a99078a7602fa1e425 [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef MSS_IPC_DRV_H
9#define MSS_IPC_DRV_H
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/psci/psci.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]12
13#define MV_PM_FW_IPC_VERSION_MAGIC (0xCA530000) /* Do NOT change */
14/* Increament for each version */
15#define MV_PM_FW_IPC_VERSION_SEQ (0x00000001)
16#define MV_PM_FW_IPC_VERSION (MV_PM_FW_IPC_VERSION_MAGIC | \
17 MV_PM_FW_IPC_VERSION_SEQ)
18
19#define IPC_MSG_STATE_LOC (0x0)
20#define IPC_MSG_SYNC_ID_LOC (0x4)
21#define IPC_MSG_ID_LOC (0x8)
22#define IPC_MSG_RET_CH_ID_LOC (0xC)
23#define IPC_MSG_CPU_ID_LOC (0x10)
24#define IPC_MSG_CLUSTER_ID_LOC (0x14)
25#define IPC_MSG_SYSTEM_ID_LOC (0x18)
26#define IPC_MSG_POWER_STATE_LOC (0x1C)
27#define IPC_MSG_REPLY_LOC (0x20)
28#define IPC_MSG_RESERVED_LOC (0x24)
29
30/* IPC initialization state */
31enum mss_pm_ipc_init_state {
32 IPC_UN_INITIALIZED = 1,
33 IPC_INITIALIZED = 2
34};
35
36/* IPC queue direction */
37enum mss_pm_ipc_init_msg_dir {
38 IPC_MSG_TX = 0,
39 IPC_MSG_RX = 1
40};
41
42/* IPC message state */
43enum mss_pm_ipc_msg_state {
44 IPC_MSG_FREE = 1,
45 IPC_MSG_OCCUPY = 2
46
47};
48
49/* IPC control block */
50struct mss_pm_ipc_ctrl {
51 unsigned int ctrl_base_address;
52 unsigned int msg_base_address;
53 unsigned int num_of_channels;
54 unsigned int channel_size;
55 unsigned int queue_size;
56};
57
58/* IPC message types */
59enum mss_pm_msg_id {
60 PM_IPC_MSG_CPU_SUSPEND = 1,
61 PM_IPC_MSG_CPU_OFF = 2,
62 PM_IPC_MSG_CPU_ON = 3,
63 PM_IPC_MSG_SYSTEM_RESET = 4,
64 PM_IPC_MSG_SYSTEM_SUSPEND = 5,
65 PM_IPC_MAX_MSG
66};
67
68struct mss_pm_ipc_msg {
69 unsigned int msg_sync_id; /*
70 * Sync number, validate message
71 * reply corresponding to message
72 * received
73 */
74 unsigned int msg_id; /* Message Id */
75 unsigned int ret_channel_id; /* IPC channel reply */
76 unsigned int cpu_id; /* CPU Id */
77 unsigned int cluster_id; /* Cluster Id */
78 unsigned int system_id; /* System Id */
79 unsigned int power_state;
80 unsigned int msg_reply; /* Message reply */
81};
82
83/* IPC queue */
84struct mss_pm_ipc_queue {
85 unsigned int state;
86 struct mss_pm_ipc_msg msg;
87};
88
89/* IPC channel */
90struct mss_pm_ipc_ch {
91 struct mss_pm_ipc_queue *tx_queue;
92 struct mss_pm_ipc_queue *rx_queue;
93};
94
95/*****************************************************************************
96 * mv_pm_ipc_init
97 *
98 * DESCRIPTION: Initialize PM IPC infrastructure
99 *****************************************************************************
100 */
101int mv_pm_ipc_init(unsigned long ipc_control_addr);
102
103/*****************************************************************************
104 * mv_pm_ipc_msg_rx
105 *
106 * DESCRIPTION: Retrieve message from IPC channel
107 *****************************************************************************
108 */
109int mv_pm_ipc_msg_rx(unsigned int channel_id, struct mss_pm_ipc_msg *msg);
110
111/*****************************************************************************
112 * mv_pm_ipc_msg_tx
113 *
114 * DESCRIPTION: Send message via IPC channel
115 *****************************************************************************
116 */
117int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id,
118 unsigned int cluster_power_state);
119
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]120#endif /* MSS_IPC_DRV_H */