| Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 1 | /* |
| Sona Mathew | 9516858 | 2023-09-05 14:10:03 -0500 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Arm Limited. All rights reserved. |
| Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_X3_H |
| 8 | #define CORTEX_X3_H |
| 9 | |
| 10 | #define CORTEX_X3_MIDR U(0x410FD4E0) |
| 11 | |
| 12 | /* Cortex-X3 loop count for CVE-2022-23960 mitigation */ |
| Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 13 | #define CORTEX_X3_BHB_LOOP_COUNT U(132) |
| Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 19 | |
| 20 | /******************************************************************************* |
| 21 | * CPU Power Control register specific definitions |
| 22 | ******************************************************************************/ |
| Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 23 | #define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 24 | #define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 25 | #define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) |
| 26 | #define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) |
| Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 27 | |
| Boyan Karatotev | 6559dbd | 2022-10-03 14:18:28 +0100 | [diff] [blame] | 28 | /******************************************************************************* |
| 29 | * CPU Auxiliary Control register 2 specific definitions. |
| 30 | ******************************************************************************/ |
| 31 | #define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 32 | #define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) |
| 33 | |
| Sona Mathew | 9516858 | 2023-09-05 14:10:03 -0500 | [diff] [blame] | 34 | /******************************************************************************* |
| 35 | * CPU Auxiliary Control register 5 specific definitions. |
| 36 | ******************************************************************************/ |
| 37 | #define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| 38 | #define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) |
| 39 | #define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) |
| 40 | |
| Sona Mathew | 35c7d39 | 2023-10-03 17:09:09 -0500 | [diff] [blame] | 41 | /******************************************************************************* |
| 42 | * CPU Extended Control register 2 specific definitions. |
| 43 | ******************************************************************************/ |
| 44 | #define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 45 | |
| 46 | #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) |
| 47 | #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| 48 | #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) |
| 49 | |
| Sona Mathew | 2eab9d0 | 2023-11-06 13:48:22 -0600 | [diff] [blame] | 50 | /******************************************************************************* |
| 51 | * CPU Auxiliary Control register 3 specific definitions. |
| 52 | ******************************************************************************/ |
| 53 | #define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2 |
| 54 | #define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) |
| 55 | |
| Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 56 | #endif /* CORTEX_X3_H */ |