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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_H__
32#define __PLATFORM_H__
33
34#include <arch.h>
35#include <mmio.h>
36#include <psci.h>
37#include <bl_common.h>
38
39
40/*******************************************************************************
41 * Platform binary types for linking
42 ******************************************************************************/
43#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
44#define PLATFORM_LINKER_ARCH aarch64
45
46/*******************************************************************************
47 * Generic platform constants
48 ******************************************************************************/
49#define PLATFORM_STACK_SIZE 0x800
50
51#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
52#define BL2_IMAGE_NAME "bl2.bin"
53#define BL31_IMAGE_NAME "bl31.bin"
54#define NS_IMAGE_OFFSET FLASH0_BASE
55
56#define PLATFORM_CACHE_LINE_SIZE 64
57#define PLATFORM_CLUSTER_COUNT 2ull
58#define PLATFORM_CLUSTER0_CORE_COUNT 4
59#define PLATFORM_CLUSTER1_CORE_COUNT 4
Ian Spray84687392014-01-02 16:57:12 +000060#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
61 PLATFORM_CLUSTER0_CORE_COUNT)
Achin Gupta4f6ad662013-10-25 09:08:21 +010062#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
63#define PRIMARY_CPU 0x0
64
65/* Constants for accessing platform configuration */
66#define CONFIG_GICD_ADDR 0
67#define CONFIG_GICC_ADDR 1
68#define CONFIG_GICH_ADDR 2
69#define CONFIG_GICV_ADDR 3
70#define CONFIG_MAX_AFF0 4
71#define CONFIG_MAX_AFF1 5
72/* Indicate whether the CPUECTLR SMP bit should be enabled. */
73#define CONFIG_CPU_SETUP 6
74#define CONFIG_BASE_MMAP 7
Harry Liebel30affd52013-10-30 17:41:48 +000075/* Indicates whether CCI should be enabled on the platform. */
76#define CONFIG_HAS_CCI 8
77#define CONFIG_LIMIT 9
Achin Gupta4f6ad662013-10-25 09:08:21 +010078
79/*******************************************************************************
80 * Platform memory map related constants
81 ******************************************************************************/
82#define TZROM_BASE 0x00000000
83#define TZROM_SIZE 0x04000000
84
85#define TZRAM_BASE 0x04000000
86#define TZRAM_SIZE 0x40000
87
88#define FLASH0_BASE 0x08000000
89#define FLASH0_SIZE TZROM_SIZE
90
91#define FLASH1_BASE 0x0c000000
92#define FLASH1_SIZE 0x04000000
93
94#define PSRAM_BASE 0x14000000
95#define PSRAM_SIZE 0x04000000
96
97#define VRAM_BASE 0x18000000
98#define VRAM_SIZE 0x02000000
99
100/* Aggregate of all devices in the first GB */
101#define DEVICE0_BASE 0x1a000000
102#define DEVICE0_SIZE 0x12200000
103
104#define DEVICE1_BASE 0x2f000000
105#define DEVICE1_SIZE 0x200000
106
107#define NSRAM_BASE 0x2e000000
108#define NSRAM_SIZE 0x10000
109
110/* Location of trusted dram on the base fvp */
111#define TZDRAM_BASE 0x06000000
112#define TZDRAM_SIZE 0x02000000
113#define MBOX_OFF 0x1000
114#define AFFMAP_OFF 0x1200
115
116#define DRAM_BASE 0x80000000ull
117#define DRAM_SIZE 0x80000000ull
118
119#define PCIE_EXP_BASE 0x40000000
120#define TZRNG_BASE 0x7fe60000
121#define TZNVCTR_BASE 0x7fe70000
122#define TZROOTKEY_BASE 0x7fe80000
123
124/* Memory mapped Generic timer interfaces */
125#define SYS_CNTCTL_BASE 0x2a430000
126#define SYS_CNTREAD_BASE 0x2a800000
127#define SYS_TIMCTL_BASE 0x2a810000
128
129/* Counter timer module offsets */
130#define CNTNSAR 0x4
131#define CNTNSAR_NS_SHIFT(x) x
132
133#define CNTACR_BASE(x) (0x40 + (x << 2))
134#define CNTACR_RPCT_SHIFT 0x0
135#define CNTACR_RVCT_SHIFT 0x1
136#define CNTACR_RFRQ_SHIFT 0x2
137#define CNTACR_RVOFF_SHIFT 0x3
138#define CNTACR_RWVT_SHIFT 0x4
139#define CNTACR_RWPT_SHIFT 0x5
140
141/* V2M motherboard system registers & offsets */
142#define VE_SYSREGS_BASE 0x1c010000
143#define V2M_SYS_ID 0x0
144#define V2M_SYS_LED 0x8
145#define V2M_SYS_CFGDATA 0xa0
146#define V2M_SYS_CFGCTRL 0xa4
147
148/*
149 * V2M sysled bit definitions. The values written to this
150 * register are defined in arch.h & runtime_svc.h. Only
151 * used by the primary cpu to diagnose any cold boot issues.
152 *
153 * SYS_LED[0] - Security state (S=0/NS=1)
154 * SYS_LED[2:1] - Exception Level (EL3-EL0)
155 * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
156 *
157 */
158#define SYS_LED_SS_SHIFT 0x0
159#define SYS_LED_EL_SHIFT 0x1
160#define SYS_LED_EC_SHIFT 0x3
161
162#define SYS_LED_SS_MASK 0x1
163#define SYS_LED_EL_MASK 0x3
164#define SYS_LED_EC_MASK 0x1f
165
166/* V2M sysid register bits */
167#define SYS_ID_REV_SHIFT 27
168#define SYS_ID_HBI_SHIFT 16
169#define SYS_ID_BLD_SHIFT 12
170#define SYS_ID_ARCH_SHIFT 8
171#define SYS_ID_FPGA_SHIFT 0
172
173#define SYS_ID_REV_MASK 0xf
174#define SYS_ID_HBI_MASK 0xfff
175#define SYS_ID_BLD_MASK 0xf
176#define SYS_ID_ARCH_MASK 0xf
177#define SYS_ID_FPGA_MASK 0xff
178
179#define SYS_ID_BLD_LENGTH 4
180
181#define REV_FVP 0x0
182#define HBI_FVP_BASE 0x020
183#define HBI_FOUNDATION 0x010
184
185#define BLD_GIC_VE_MMAP 0x0
186#define BLD_GIC_A53A57_MMAP 0x1
187
188#define ARCH_MODEL 0x1
189
190/* FVP Power controller base address*/
191#define PWRC_BASE 0x1c100000
192
193/*******************************************************************************
194 * Platform specific per affinity states. Distinction between off and suspend
195 * is made to allow reporting of a suspended cpu as still being on e.g. in the
196 * affinity_info psci call.
197 ******************************************************************************/
198#define PLATFORM_MAX_AFF0 4
199#define PLATFORM_MAX_AFF1 2
200#define PLAT_AFF_UNK 0xff
201
202#define PLAT_AFF0_OFF 0x0
203#define PLAT_AFF0_ONPENDING 0x1
204#define PLAT_AFF0_SUSPEND 0x2
205#define PLAT_AFF0_ON 0x3
206
207#define PLAT_AFF1_OFF 0x0
208#define PLAT_AFF1_ONPENDING 0x1
209#define PLAT_AFF1_SUSPEND 0x2
210#define PLAT_AFF1_ON 0x3
211
212/*******************************************************************************
213 * BL2 specific defines.
214 ******************************************************************************/
215#define BL2_BASE 0x0402D000
216
217/*******************************************************************************
218 * BL31 specific defines.
219 ******************************************************************************/
220#define BL31_BASE 0x0400E000
221
222/*******************************************************************************
223 * Platform specific page table and MMU setup constants
224 ******************************************************************************/
225#define EL3_ADDR_SPACE_SIZE (1ull << 32)
226#define EL3_NUM_PAGETABLES 2
227#define EL3_TROM_PAGETABLE 0
228#define EL3_TRAM_PAGETABLE 1
229
230#define ADDR_SPACE_SIZE (1ull << 32)
231
232#define NUM_L2_PAGETABLES 2
233#define GB1_L2_PAGETABLE 0
234#define GB2_L2_PAGETABLE 1
235
236#define NUM_L3_PAGETABLES 2
237#define TZRAM_PAGETABLE 0
238#define NSRAM_PAGETABLE 1
239
240/*******************************************************************************
241 * CCI-400 related constants
242 ******************************************************************************/
243#define CCI400_BASE 0x2c090000
244#define CCI400_SL_IFACE_CLUSTER0 3
245#define CCI400_SL_IFACE_CLUSTER1 4
246#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
247 CCI400_SL_IFACE_CLUSTER1 : \
248 CCI400_SL_IFACE_CLUSTER0)
249
250/*******************************************************************************
251 * GIC-400 & interrupt handling related constants
252 ******************************************************************************/
253/* VE compatible GIC memory map */
254#define VE_GICD_BASE 0x2c001000
255#define VE_GICC_BASE 0x2c002000
256#define VE_GICH_BASE 0x2c004000
257#define VE_GICV_BASE 0x2c006000
258
259/* Base FVP compatible GIC memory map */
260#define BASE_GICD_BASE 0x2f000000
261#define BASE_GICR_BASE 0x2f100000
262#define BASE_GICC_BASE 0x2c000000
263#define BASE_GICH_BASE 0x2c010000
264#define BASE_GICV_BASE 0x2c02f000
265
266#define IRQ_TZ_WDOG 56
267#define IRQ_SEC_PHY_TIMER 29
268#define IRQ_SEC_SGI_0 8
269#define IRQ_SEC_SGI_1 9
270#define IRQ_SEC_SGI_2 10
271#define IRQ_SEC_SGI_3 11
272#define IRQ_SEC_SGI_4 12
273#define IRQ_SEC_SGI_5 13
274#define IRQ_SEC_SGI_6 14
275#define IRQ_SEC_SGI_7 15
276#define IRQ_SEC_SGI_8 16
277
278/*******************************************************************************
279 * PL011 related constants
280 ******************************************************************************/
281#define PL011_BASE 0x1c090000
282
283/*******************************************************************************
284 * Declarations and constants to access the mailboxes safely. Each mailbox is
285 * aligned on the biggest cache line size in the platform. This is known only
286 * to the platform as it might have a combination of integrated and external
287 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
288 * line at any cache level. They could belong to different cpus/clusters &
289 * get written while being protected by different locks causing corruption of
290 * a valid mailbox address.
291 ******************************************************************************/
292#define CACHE_WRITEBACK_SHIFT 6
293#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
294
295#ifndef __ASSEMBLY__
296
297typedef volatile struct {
298 unsigned long value
299 __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
300} mailbox;
301
302/*******************************************************************************
303 * Function and variable prototypes
304 ******************************************************************************/
305extern unsigned long *bl1_normal_ram_base;
306extern unsigned long *bl1_normal_ram_len;
307extern unsigned long *bl1_normal_ram_limit;
308extern unsigned long *bl1_normal_ram_zi_base;
309extern unsigned long *bl1_normal_ram_zi_len;
310
311extern unsigned long *bl1_coherent_ram_base;
312extern unsigned long *bl1_coherent_ram_len;
313extern unsigned long *bl1_coherent_ram_limit;
314extern unsigned long *bl1_coherent_ram_zi_base;
315extern unsigned long *bl1_coherent_ram_zi_len;
316extern unsigned long warm_boot_entrypoint;
317
318extern void bl1_plat_arch_setup(void);
319extern void bl2_plat_arch_setup(void);
320extern void bl31_plat_arch_setup(void);
321extern int platform_setup_pm(plat_pm_ops **);
322extern unsigned int platform_get_core_pos(unsigned long mpidr);
323extern void disable_mmu(void);
324extern void enable_mmu(void);
325extern void configure_mmu(meminfo *,
326 unsigned long,
327 unsigned long,
328 unsigned long,
329 unsigned long);
330extern unsigned long platform_get_cfgvar(unsigned int);
331extern int platform_config_setup(void);
332extern void plat_report_exception(unsigned long);
333extern unsigned long plat_get_ns_image_entrypoint(void);
Achin Guptac8afc782013-11-25 18:45:02 +0000334extern unsigned long platform_get_stack(unsigned long mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100335
Ian Spray84687392014-01-02 16:57:12 +0000336/* Declarations for fvp_gic.c */
337extern void gic_cpuif_deactivate(unsigned int);
338extern void gic_cpuif_setup(unsigned int);
339extern void gic_pcpu_distif_setup(unsigned int);
340extern void gic_setup(void);
341
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342/* Declarations for fvp_topology.c */
343extern int plat_setup_topology(void);
344extern int plat_get_max_afflvl(void);
345extern unsigned int plat_get_aff_count(unsigned int, unsigned long);
346extern unsigned int plat_get_aff_state(unsigned int, unsigned long);
347
348#endif /*__ASSEMBLY__*/
349
350#endif /* __PLATFORM_H__ */