blob: 30bd4fc272891a71838871427ac0fd69976839c9 [file] [log] [blame]
Sandrine Bailleux27866d82013-10-25 15:33:39 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux27866d82013-10-25 15:33:39 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GIC_V2_H__
32#define __GIC_V2_H__
33
34#include <mmio.h>
35
36/*******************************************************************************
37 * GIC Distributor interface accessors for reading entire registers
38 ******************************************************************************/
39
40static inline unsigned int gicd_read_ctlr(unsigned int base)
41{
42 return mmio_read_32(base + GICD_CTLR);
43}
44
45static inline unsigned int gicd_read_typer(unsigned int base)
46{
47 return mmio_read_32(base + GICD_TYPER);
48}
49
50static inline unsigned int gicd_read_sgir(unsigned int base)
51{
52 return mmio_read_32(base + GICD_SGIR);
53}
54
55
56/*******************************************************************************
57 * GIC Distributor interface accessors for writing entire registers
58 ******************************************************************************/
59
60static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
61{
62 mmio_write_32(base + GICD_CTLR, val);
63}
64
65static inline void gicd_write_sgir(unsigned int base, unsigned int val)
66{
67 mmio_write_32(base + GICD_SGIR, val);
68}
69
70
71/*******************************************************************************
72 * GIC CPU interface accessors for reading entire registers
73 ******************************************************************************/
74
75static inline unsigned int gicc_read_ctlr(unsigned int base)
76{
77 return mmio_read_32(base + GICC_CTLR);
78}
79
80static inline unsigned int gicc_read_pmr(unsigned int base)
81{
82 return mmio_read_32(base + GICC_PMR);
83}
84
85static inline unsigned int gicc_read_BPR(unsigned int base)
86{
87 return mmio_read_32(base + GICC_BPR);
88}
89
90static inline unsigned int gicc_read_IAR(unsigned int base)
91{
92 return mmio_read_32(base + GICC_IAR);
93}
94
95static inline unsigned int gicc_read_EOIR(unsigned int base)
96{
97 return mmio_read_32(base + GICC_EOIR);
98}
99
100static inline unsigned int gicc_read_hppir(unsigned int base)
101{
102 return mmio_read_32(base + GICC_HPPIR);
103}
104
105static inline unsigned int gicc_read_dir(unsigned int base)
106{
107 return mmio_read_32(base + GICC_DIR);
108}
109
110static inline unsigned int gicc_read_iidr(unsigned int base)
111{
112 return mmio_read_32(base + GICC_IIDR);
113}
114
115
116/*******************************************************************************
117 * GIC CPU interface accessors for writing entire registers
118 ******************************************************************************/
119
120static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
121{
122 mmio_write_32(base + GICC_CTLR, val);
123}
124
125static inline void gicc_write_pmr(unsigned int base, unsigned int val)
126{
127 mmio_write_32(base + GICC_PMR, val);
128}
129
130static inline void gicc_write_BPR(unsigned int base, unsigned int val)
131{
132 mmio_write_32(base + GICC_BPR, val);
133}
134
135
136static inline void gicc_write_IAR(unsigned int base, unsigned int val)
137{
138 mmio_write_32(base + GICC_IAR, val);
139}
140
141static inline void gicc_write_EOIR(unsigned int base, unsigned int val)
142{
143 mmio_write_32(base + GICC_EOIR, val);
144}
145
146static inline void gicc_write_hppir(unsigned int base, unsigned int val)
147{
148 mmio_write_32(base + GICC_HPPIR, val);
149}
150
151static inline void gicc_write_dir(unsigned int base, unsigned int val)
152{
153 mmio_write_32(base + GICC_DIR, val);
154}
155
156#endif /* __GIC_V2_H__ */