Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __BOARD_ARM_DEF_H__ |
| 7 | #define __BOARD_ARM_DEF_H__ |
| 8 | |
| 9 | #include <v2m_def.h> |
| 10 | |
| 11 | |
| 12 | /* |
| 13 | * Required platform porting definitions common to all ARM |
| 14 | * development platforms |
| 15 | */ |
| 16 | |
| 17 | /* Size of cacheable stacks */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 18 | #if defined(IMAGE_BL1) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 19 | #if TRUSTED_BOARD_BOOT |
| 20 | # define PLATFORM_STACK_SIZE 0x1000 |
| 21 | #else |
| 22 | # define PLATFORM_STACK_SIZE 0x440 |
| 23 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 24 | #elif defined(IMAGE_BL2) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 25 | # if TRUSTED_BOARD_BOOT |
| 26 | # define PLATFORM_STACK_SIZE 0x1000 |
| 27 | # else |
| 28 | # define PLATFORM_STACK_SIZE 0x400 |
| 29 | # endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 30 | #elif defined(IMAGE_BL2U) |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 31 | # define PLATFORM_STACK_SIZE 0x200 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 32 | #elif defined(IMAGE_BL31) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 33 | # define PLATFORM_STACK_SIZE 0x400 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 34 | #elif defined(IMAGE_BL32) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 35 | # define PLATFORM_STACK_SIZE 0x440 |
| 36 | #endif |
| 37 | |
| 38 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 39 | * The constants below are not optimised for memory usage. Platforms that wish |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 40 | * to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 41 | * provide there own values. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 42 | */ |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 43 | #if !ARM_BOARD_OPTIMISE_MEM |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 44 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 45 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 46 | * plat_arm_mmap array defined for each BL stage. |
| 47 | * |
| 48 | * Provide relatively optimised values for the runtime images (BL31 and BL32). |
| 49 | * Optimisation is less important for the other, transient boot images so a |
| 50 | * common, maximum value is used across these images. |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 51 | * |
| 52 | * They are also used for the dynamically mapped regions in the images that |
| 53 | * enable dynamic memory mapping. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 54 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 55 | #if defined(IMAGE_BL31) || defined(IMAGE_BL32) |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 56 | # define PLAT_ARM_MMAP_ENTRIES 6 |
David Cunado | c3bd8c2 | 2017-10-05 21:24:14 +0100 | [diff] [blame] | 57 | # define MAX_XLAT_TABLES 5 |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 58 | #else |
David Cunado | c3bd8c2 | 2017-10-05 21:24:14 +0100 | [diff] [blame] | 59 | # define PLAT_ARM_MMAP_ENTRIES 11 |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 60 | # define MAX_XLAT_TABLES 5 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 61 | #endif |
| 62 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 63 | /* |
| 64 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 65 | * plus a little space for growth. |
| 66 | */ |
Qixiang Xu | a674feb | 2017-08-24 14:28:08 +0800 | [diff] [blame] | 67 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 71 | * little space for growth. |
| 72 | */ |
| 73 | #if TRUSTED_BOARD_BOOT |
| 74 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 75 | #else |
| 76 | # define PLAT_ARM_MAX_BL2_SIZE 0xF000 |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 81 | * little space for growth. |
| 82 | */ |
| 83 | #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 |
| 84 | |
| 85 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 86 | |
| 87 | #define MAX_IO_DEVICES 3 |
| 88 | #define MAX_IO_HANDLES 4 |
| 89 | |
| 90 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 91 | |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 92 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 93 | #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 94 | #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 95 | |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 96 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 97 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 98 | |
| 99 | /* PSCI memory protect definitions: |
| 100 | * This variable is stored in a non-secure flash because some ARM reference |
| 101 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 102 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 103 | */ |
| 104 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 105 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 106 | |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 107 | /* |
| 108 | * Map mem_protect flash region with read and write permissions |
| 109 | */ |
| 110 | #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ |
| 111 | V2M_FLASH_BLOCK_SIZE, \ |
| 112 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 113 | |
| 114 | #endif /* __BOARD_ARM_DEF_H__ */ |