Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
David Cunado | 2e36de8 | 2017-01-19 10:26:16 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __COMMON_DEF_H__ |
| 7 | #define __COMMON_DEF_H__ |
| 8 | |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 9 | #include <bl_common.h> |
| 10 | #include <platform_def.h> |
| 11 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 12 | /****************************************************************************** |
| 13 | * Required platform porting definitions that are expected to be common to |
| 14 | * all platforms |
| 15 | *****************************************************************************/ |
| 16 | |
| 17 | /* |
| 18 | * Platform binary types for linking |
| 19 | */ |
Yatharth Kochar | f528faf | 2016-06-28 16:58:26 +0100 | [diff] [blame] | 20 | #ifdef AARCH32 |
| 21 | #define PLATFORM_LINKER_FORMAT "elf32-littlearm" |
| 22 | #define PLATFORM_LINKER_ARCH arm |
| 23 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 24 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 25 | #define PLATFORM_LINKER_ARCH aarch64 |
Yatharth Kochar | f528faf | 2016-06-28 16:58:26 +0100 | [diff] [blame] | 26 | #endif /* AARCH32 */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 27 | |
| 28 | /* |
| 29 | * Generic platform constants |
| 30 | */ |
| 31 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 32 | |
Yatharth Kochar | 51f76f6 | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 33 | #if LOAD_IMAGE_V2 |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 34 | #define BL2_IMAGE_DESC { \ |
| 35 | .image_id = BL2_IMAGE_ID, \ |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 36 | SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ |
Yatharth Kochar | 51f76f6 | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 37 | VERSION_2, image_info_t, 0), \ |
| 38 | .image_info.image_base = BL2_BASE, \ |
| 39 | .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ |
| 40 | SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ |
| 41 | VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ |
| 42 | .ep_info.pc = BL2_BASE, \ |
| 43 | } |
| 44 | #else /* LOAD_IMAGE_V2 */ |
| 45 | #define BL2_IMAGE_DESC { \ |
| 46 | .image_id = BL2_IMAGE_ID, \ |
| 47 | SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 48 | VERSION_1, image_info_t, 0), \ |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 49 | .image_info.image_base = BL2_BASE, \ |
Yatharth Kochar | f11b29a | 2016-02-01 11:04:46 +0000 | [diff] [blame] | 50 | SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ |
| 51 | VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\ |
| 52 | .ep_info.pc = BL2_BASE, \ |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 53 | } |
Yatharth Kochar | 51f76f6 | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 54 | #endif /* LOAD_IMAGE_V2 */ |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 55 | |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 56 | /* |
| 57 | * The following constants identify the extents of the code & read-only data |
| 58 | * regions. These addresses are used by the MMU setup code and therefore they |
| 59 | * must be page-aligned. |
| 60 | * |
| 61 | * When the code and read-only data are mapped as a single atomic section |
| 62 | * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as |
| 63 | * code by specifying the read-only data section as empty. |
| 64 | * |
| 65 | * BL1 is different than the other images in the sense that its read-write data |
| 66 | * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at |
| 67 | * run-time. Therefore, the read-write data in ROM can be mapped with the same |
| 68 | * memory attributes as the read-only data region. For this reason, BL1 uses |
| 69 | * different macros. |
| 70 | * |
| 71 | * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it |
| 72 | * just points to the end of BL1's actual content in Trusted ROM. Therefore it |
| 73 | * needs to be rounded up to the next page size in order to map the whole last |
| 74 | * page of it with the right memory attributes. |
| 75 | */ |
| 76 | #if SEPARATE_CODE_AND_RODATA |
| 77 | #define BL_CODE_BASE (unsigned long)(&__TEXT_START__) |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 78 | #define BL_CODE_END (unsigned long)(&__TEXT_END__) |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 79 | #define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__) |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 80 | #define BL_RO_DATA_END (unsigned long)(&__RODATA_END__) |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 81 | |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 82 | #define BL1_CODE_END BL_CODE_END |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 83 | #define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__) |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 84 | #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 85 | #else |
| 86 | #define BL_CODE_BASE (unsigned long)(&__RO_START__) |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 87 | #define BL_CODE_END (unsigned long)(&__RO_END__) |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 88 | #define BL_RO_DATA_BASE 0 |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 89 | #define BL_RO_DATA_END 0 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 90 | |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 91 | #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 92 | #define BL1_RO_DATA_BASE 0 |
Masahiro Yamada | 51bef61 | 2017-01-18 02:10:08 +0900 | [diff] [blame] | 93 | #define BL1_RO_DATA_END 0 |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 94 | #endif /* SEPARATE_CODE_AND_RODATA */ |
| 95 | |
Masahiro Yamada | 0fac5af | 2016-12-28 16:11:41 +0900 | [diff] [blame] | 96 | /* |
| 97 | * The next 2 constants identify the extents of the coherent memory region. |
| 98 | * These addresses are used by the MMU setup code and therefore they must be |
| 99 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 100 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 101 | * page-aligned addresses. |
| 102 | */ |
| 103 | #define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 104 | #define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__) |
| 105 | |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 106 | #endif /* __COMMON_DEF_H__ */ |