blob: 57186503bba4f1f74fb40a52fa129a300900d6b2 [file] [log] [blame]
Varun Wadekar00759902017-05-31 11:41:00 -07001/*
Pritesh Raithatha45ea6892017-12-18 23:00:05 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekar00759902017-05-31 11:41:00 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Varun Wadekar128f46a2019-10-24 16:06:12 -07007#include <assert.h>
8#include <common/bl_common.h>
9#include <mce.h>
Varun Wadekar00759902017-05-31 11:41:00 -070010#include <memctrl_v2.h>
Varun Wadekar128f46a2019-10-24 16:06:12 -070011#include <tegra_mc_def.h>
12#include <tegra_platform.h>
Varun Wadekar00759902017-05-31 11:41:00 -070013
14/*******************************************************************************
15 * Array to hold stream_id override config register offsets
16 ******************************************************************************/
17const static uint32_t tegra194_streamid_override_regs[] = {
18 MC_STREAMID_OVERRIDE_CFG_HDAR,
19 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
20 MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
21 MC_STREAMID_OVERRIDE_CFG_SATAR,
22 MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
23 MC_STREAMID_OVERRIDE_CFG_HDAW,
24 MC_STREAMID_OVERRIDE_CFG_SATAW,
25 MC_STREAMID_OVERRIDE_CFG_ISPRA,
26 MC_STREAMID_OVERRIDE_CFG_ISPFALR,
27 MC_STREAMID_OVERRIDE_CFG_ISPWA,
28 MC_STREAMID_OVERRIDE_CFG_ISPWB,
29 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
30 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
31 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
32 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
33 MC_STREAMID_OVERRIDE_CFG_TSECSRD,
34 MC_STREAMID_OVERRIDE_CFG_TSECSWR,
35 MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
36 MC_STREAMID_OVERRIDE_CFG_SDMMCR,
37 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
38 MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
39 MC_STREAMID_OVERRIDE_CFG_SDMMCW,
40 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
41 MC_STREAMID_OVERRIDE_CFG_VICSRD,
42 MC_STREAMID_OVERRIDE_CFG_VICSWR,
43 MC_STREAMID_OVERRIDE_CFG_VIW,
44 MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
45 MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
46 MC_STREAMID_OVERRIDE_CFG_APER,
47 MC_STREAMID_OVERRIDE_CFG_APEW,
48 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
49 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
50 MC_STREAMID_OVERRIDE_CFG_SESRD,
51 MC_STREAMID_OVERRIDE_CFG_SESWR,
52 MC_STREAMID_OVERRIDE_CFG_AXIAPR,
53 MC_STREAMID_OVERRIDE_CFG_AXIAPW,
54 MC_STREAMID_OVERRIDE_CFG_ETRR,
55 MC_STREAMID_OVERRIDE_CFG_ETRW,
56 MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
57 MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
58 MC_STREAMID_OVERRIDE_CFG_AXISR,
59 MC_STREAMID_OVERRIDE_CFG_AXISW,
60 MC_STREAMID_OVERRIDE_CFG_EQOSR,
61 MC_STREAMID_OVERRIDE_CFG_EQOSW,
62 MC_STREAMID_OVERRIDE_CFG_UFSHCR,
63 MC_STREAMID_OVERRIDE_CFG_UFSHCW,
64 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
65 MC_STREAMID_OVERRIDE_CFG_BPMPR,
66 MC_STREAMID_OVERRIDE_CFG_BPMPW,
67 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
68 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
69 MC_STREAMID_OVERRIDE_CFG_AONR,
70 MC_STREAMID_OVERRIDE_CFG_AONW,
71 MC_STREAMID_OVERRIDE_CFG_AONDMAR,
72 MC_STREAMID_OVERRIDE_CFG_AONDMAW,
73 MC_STREAMID_OVERRIDE_CFG_SCER,
74 MC_STREAMID_OVERRIDE_CFG_SCEW,
75 MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
76 MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
77 MC_STREAMID_OVERRIDE_CFG_APEDMAR,
78 MC_STREAMID_OVERRIDE_CFG_APEDMAW,
79 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
80 MC_STREAMID_OVERRIDE_CFG_VICSRD1,
81 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
82 MC_STREAMID_OVERRIDE_CFG_VIFALR,
83 MC_STREAMID_OVERRIDE_CFG_VIFALW,
84 MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
85 MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
86 MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
87 MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
88 MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
89 MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
90 MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
91 MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
92 MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
93 MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
94 MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
95 MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
96 MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
97 MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
98 MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
99 MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
100 MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
101 MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
102 MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
103 MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
104 MC_STREAMID_OVERRIDE_CFG_RCER,
105 MC_STREAMID_OVERRIDE_CFG_RCEW,
106 MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
107 MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
108 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
109 MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
110 MC_STREAMID_OVERRIDE_CFG_PCIE0R,
111 MC_STREAMID_OVERRIDE_CFG_PCIE0W,
112 MC_STREAMID_OVERRIDE_CFG_PCIE1R,
113 MC_STREAMID_OVERRIDE_CFG_PCIE1W,
114 MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
115 MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
116 MC_STREAMID_OVERRIDE_CFG_PCIE3R,
117 MC_STREAMID_OVERRIDE_CFG_PCIE3W,
118 MC_STREAMID_OVERRIDE_CFG_PCIE4R,
119 MC_STREAMID_OVERRIDE_CFG_PCIE4W,
120 MC_STREAMID_OVERRIDE_CFG_PCIE5R,
121 MC_STREAMID_OVERRIDE_CFG_PCIE5W,
122 MC_STREAMID_OVERRIDE_CFG_ISPFALW,
123 MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
124 MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
125 MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
126 MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
127 MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
128 MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
129 MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
130 MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
131 MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
132 MC_STREAMID_OVERRIDE_CFG_ISPRA1,
133 MC_STREAMID_OVERRIDE_CFG_MIU0R,
134 MC_STREAMID_OVERRIDE_CFG_MIU0W,
135 MC_STREAMID_OVERRIDE_CFG_MIU1R,
136 MC_STREAMID_OVERRIDE_CFG_MIU1W,
137 MC_STREAMID_OVERRIDE_CFG_MIU2R,
138 MC_STREAMID_OVERRIDE_CFG_MIU2W,
139 MC_STREAMID_OVERRIDE_CFG_MIU3R,
140 MC_STREAMID_OVERRIDE_CFG_MIU3W
141};
142
143/*******************************************************************************
144 * Array to hold the security configs for stream IDs
145 ******************************************************************************/
146const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
147 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
148 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
149 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
150 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
151 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
152 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
153 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
154 mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
155 mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
156 mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
157 mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
Ajay Gupta81621092017-08-01 15:53:04 -0700158 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
159 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
160 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
161 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
Varun Wadekar00759902017-05-31 11:41:00 -0700162 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
163 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
164 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
165 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
166 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
167 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
168 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
169 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
170 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
171 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
172 mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
173 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
174 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
175 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
176 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
177 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
178 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
179 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
180 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
181 mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
182 mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
183 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
184 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
185 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
186 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
187 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
188 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
189 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
190 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
191 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
192 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
193 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
194 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
195 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
196 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
197 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
198 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
199 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
200 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
201 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
202 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
203 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
204 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
205 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
206 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
207 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
208 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
209 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
210 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
211 mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
212 mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
213 mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
214 mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
215 mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
216 mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
217 mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
218 mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
219 mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
220 mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
221 mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
222 mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
223 mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
224 mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
225 mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
226 mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
227 mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
228 mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
229 mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
230 mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
231 mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
232 mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
233 mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
234 mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
235 mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
236 mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
237 mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
238 mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
239 mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
240 mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
241 mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
242 mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
243 mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
244 mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
245 mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
246 mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
247 mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
248 mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
249 mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
250 mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
251 mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
252 mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
253 mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
254 mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
255 mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
256 mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
257 mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
258 mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
259 mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
260 mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
261 mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
262 mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
263 mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
264 mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
265 mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
266 mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
267 mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
268 mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
269 mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
270};
271
272/*******************************************************************************
273 * Array to hold the transaction override configs
274 ******************************************************************************/
275const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = {
276 mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
277 mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
278 mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
279 mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
280 mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
281 mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
282 mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
283 mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
284 mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
285 mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
286 mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
287 mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
288 mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
289 mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
290 mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
291 mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
292 mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
293 mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
294 mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
295 mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
296 mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
297 mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
298 mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
299 mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
300 mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
301 mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
302};
303
Varun Wadekar128f46a2019-10-24 16:06:12 -0700304/* To be called by common memctrl_v2.c */
305static void tegra194_memctrl_reconfig_mss_clients(void)
306{
307 uint32_t reg_val, wdata_0, wdata_1, wdata_2;
308
309 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
310 MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
311 MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
312 MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
313 MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
314 MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
315 MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
316 if (tegra_platform_is_silicon()) {
317 wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
318 }
319
320 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
321
322 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
323 do {
324 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
325 } while ((reg_val & wdata_0) != wdata_0);
326
327 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
328 MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
329 MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
330 MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
331 MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
332 MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
333 MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
334 MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
335 MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
336 MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
337 MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
338 if (tegra_platform_is_silicon()) {
339 wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
340 MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
341 MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
342 }
343 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
344 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
345 do {
346 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
347 } while ((reg_val & wdata_1) != wdata_1);
348
349 wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
350 MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
351 MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
352 MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
353 if (tegra_platform_is_silicon()) {
354 wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
355 MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
356 MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
357 MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
358 MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
359 MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
360 MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
361 MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
362 }
363 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
364 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
365 do {
366 reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
367 } while ((reg_val & wdata_2) != wdata_2);
368
369 /*
370 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
371 * strongly ordered MSS clients.
372 *
373 * MC clients with default SO_DEV override still enabled at TSA:
374 * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
375 * PCIe3w, PCIe4w and PCIe5w.
376 */
377 mc_set_tsa_w_passthrough(AONDMAW);
378 mc_set_tsa_w_passthrough(AONW);
379 mc_set_tsa_w_passthrough(APEDMAW);
380 mc_set_tsa_w_passthrough(APEW);
381 mc_set_tsa_w_passthrough(AXISW);
382 mc_set_tsa_w_passthrough(BPMPDMAW);
383 mc_set_tsa_w_passthrough(BPMPW);
384 mc_set_tsa_w_passthrough(ETRW);
385 mc_set_tsa_w_passthrough(SCEDMAW);
386 mc_set_tsa_w_passthrough(RCEDMAW);
387 mc_set_tsa_w_passthrough(RCEW);
388 mc_set_tsa_w_passthrough(SDMMCW);
389 mc_set_tsa_w_passthrough(SDMMCWA);
390 mc_set_tsa_w_passthrough(SDMMCWAB);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700391 mc_set_tsa_w_passthrough(TSECSWR);
392 mc_set_tsa_w_passthrough(TSECSWRB);
393 mc_set_tsa_w_passthrough(UFSHCW);
394 mc_set_tsa_w_passthrough(VICSWR);
395 mc_set_tsa_w_passthrough(VIFALW);
396
397 /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
398 * ISO clients(DISP, VI, EQOS) should never snoop caches and
399 * don't need ROC/PCFIFO ordering.
400 * ISO clients(EQOS) that need ordering should use PCFIFO ordering
401 * and bypass ROC ordering by using FORCE_NON_COHERENT path.
402 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
403 * over SMMU attributes.
404 * Force all Normal memory transactions from ISO and non-ISO to be
405 * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
406 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
407 * non-coherent path and enable MC PCFIFO interlock for ordering.
408 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
409 * XUSB, SATA) to coherent so that the transactions are
410 * ordered by ROC.
411 * PCFIFO ensure write ordering.
412 * Read after Write ordering is maintained/enforced by MC clients.
413 * Clients that need PCIe type write ordering must
414 * go through ROC ordering.
415 * Ordering enable for Read clients is not necessary.
416 * R5's and A9 would get necessary ordering from AXI and
417 * don't need ROC ordering enable:
418 * - MMIO ordering is through dev mapping and MMIO
419 * accesses bypass SMMU.
420 * - Normal memory is accessed through SMMU and ordering is
421 * ensured by client and AXI.
422 * - Ack point for Normal memory is WCAM in MC.
423 * - MMIO's can be early acked and AXI ensures dev memory ordering,
424 * Client ensures read/write direction change ordering.
425 * - See Bug 200312466 for more details.
426 *
427 * CGID_TAG_ADR is only present from T186 A02. As this code is common
428 * between A01 and A02, tegra_memctrl_set_overrides() programs
429 * CGID_TAG_ADR for the necessary clients on A02.
430 */
431 mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
432 mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
433 mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
434 mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
435 mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
436 mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
437 mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
438 mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
439 mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
440 mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
441 mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
442 mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
443 mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
444 mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
445 mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
446 mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
447 mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
448 mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
449 mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
450 mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
451 mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
452 mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
453 mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
454 mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
455 mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
456 mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
457 mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
458 mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
459 mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
460 mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
461 mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
462 mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
463 mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
464 mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
465 mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
466 mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
467 mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
468 mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
469 mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
Puneet Saxena0d424112017-09-08 12:14:03 +0530470 mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
471 mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700472 mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
473 mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
474 mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
475 mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
476 mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
477 mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
478 mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
479 mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
480 mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
Krishna Reddy3d8d2ab2017-12-22 20:17:09 -0800481 mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
482 mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
483 mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700484 mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
485 mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
486 FORCE_COHERENT_SNOOP);
487 mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
488 mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
489 FORCE_COHERENT_SNOOP);
490 mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
491 mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
492 mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
493 FORCE_COHERENT_SNOOP);
494 mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
495 mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
496 FORCE_COHERENT_SNOOP);
497 if (tegra_platform_is_silicon()) {
498 mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO,
499 NO_OVERRIDE, NO_OVERRIDE);
500 mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO,
501 FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
502 mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
503 NO_OVERRIDE, NO_OVERRIDE);
504 mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
505 FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
506 mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
507 NO_OVERRIDE, NO_OVERRIDE);
508 mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
509 FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
510 mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
511 NO_OVERRIDE, NO_OVERRIDE);
512 mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
513 FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
514 mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO,
515 NO_OVERRIDE, NO_OVERRIDE);
516 }
517 /*
518 * At this point, ordering can occur at ROC. So, remove PCFIFO's
519 * control over ordering requests.
520 *
521 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
522 * boot and strongly ordered MSS clients
523 */
524 /* SATAW is ordered client */
525 reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL |
526 mc_set_pcfifo_ordered_boot_so_mss(1, SATAW);
527 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val);
528
529 reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
530 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
531 mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
532 /* XUSB_DEVW has PCFIFO enabled. */
533 reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW);
534 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
535
536 reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
537 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
538 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
539 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
540 mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
541 mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
542 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
543
544 reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
545 mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
546 mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
547 mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
548 mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
549 mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
550 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
551 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
552 mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
553 mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
554 mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
555 mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
556 /* EQOSW has PCFIFO order enabled. */
557 reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
558 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
559
560 reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
561 mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
562 mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
563 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
564
565 reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
566 mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
567 mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
568 mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
569 /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */
570 reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) |
571 mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) |
572 mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W);
573 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
574
575 reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
576 mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
577 mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
578 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
579
580 /* Set Order Id only for the clients having non zero order id */
Krishna Reddya1673b32017-12-17 16:21:47 -0800581 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700582 tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
583
Krishna Reddya1673b32017-12-17 16:21:47 -0800584 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700585 tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
586
Krishna Reddya1673b32017-12-17 16:21:47 -0800587 reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W);
588 reg_val = mc_client_order_id(reg_val, 28, PCIE5W);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700589 tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
590
Krishna Reddy3d8d2ab2017-12-22 20:17:09 -0800591 /*
592 * Set VC Id only for the clients having different reset values like
593 * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and
594 * TSECSWRB clients
595 */
596 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700597 tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
598
Varun Wadekar128f46a2019-10-24 16:06:12 -0700599 /* SDMMCRAB and SDMMCWAB clients */
Krishna Reddy3d8d2ab2017-12-22 20:17:09 -0800600 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700601 tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
602
Krishna Reddy3d8d2ab2017-12-22 20:17:09 -0800603 reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700604 tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
605
606 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
607 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
608
609 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
610 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
611
612 wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
613 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
Pritesh Raithatha45ea6892017-12-18 23:00:05 -0800614
615 reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
616 tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
Varun Wadekar128f46a2019-10-24 16:06:12 -0700617}
618
Varun Wadekar00759902017-05-31 11:41:00 -0700619/*******************************************************************************
620 * Struct to hold the memory controller settings
621 ******************************************************************************/
622static tegra_mc_settings_t tegra194_mc_settings = {
623 .streamid_override_cfg = tegra194_streamid_override_regs,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800624 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
Varun Wadekar00759902017-05-31 11:41:00 -0700625 .streamid_security_cfg = tegra194_streamid_sec_cfgs,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800626 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
Varun Wadekar00759902017-05-31 11:41:00 -0700627 .txn_override_cfg = tegra194_txn_override_cfgs,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800628 .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs),
Varun Wadekar128f46a2019-10-24 16:06:12 -0700629 .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
Varun Wadekar00759902017-05-31 11:41:00 -0700630};
631
632/*******************************************************************************
633 * Handler to return the pointer to the memory controller's settings struct
634 ******************************************************************************/
635tegra_mc_settings_t *tegra_get_mc_settings(void)
636{
637 return &tegra194_mc_settings;
Steven Kaoee93ed12017-11-14 19:12:58 +0800638}
639
640/*******************************************************************************
641 * Handler to program the scratch registers with TZDRAM settings for the
642 * resume firmware
643 ******************************************************************************/
644void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
645{
Steven Kaob2b43052017-11-30 11:53:29 +0800646 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
647
Steven Kaoee93ed12017-11-14 19:12:58 +0800648 /*
Steven Kaob2b43052017-11-30 11:53:29 +0800649 * Check TZDRAM carveout register access status. Setup TZDRAM fence
650 * only if access is enabled.
Steven Kaoee93ed12017-11-14 19:12:58 +0800651 */
Steven Kaob2b43052017-11-30 11:53:29 +0800652 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
653 SECURITY_CFG_WRITE_ACCESS_ENABLE) {
Steven Kaoee93ed12017-11-14 19:12:58 +0800654
655 /*
656 * Setup the Memory controller to allow only secure accesses to
657 * the TZDRAM carveout
658 */
659 INFO("Configuring TrustZone DRAM Memory Carveout\n");
660
661 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
662 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
663 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
664
665 /*
666 * MCE propagates the security configuration values across the
667 * CCPLEX.
668 */
669 (void)mce_update_gsc_tzdram();
670 }
671}