Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 2 | * Copyright 2021-2022 NXP |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef SOC_DEFAULT_BASE_ADDR_H |
| 9 | #define SOC_DEFAULT_BASE_ADDR_H |
| 10 | |
| 11 | /* CCSR mmu_def.h */ |
| 12 | #define NXP_CCSR_ADDR 0x1000000 |
| 13 | #define NXP_CCSR_SIZE 0xF000000 |
| 14 | |
| 15 | #define NXP_DCSR_ADDR 0x700000000 |
| 16 | #define NXP_DCSR_SIZE 0x40000000 |
| 17 | |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 18 | /* Quad SPI Region #1 base address */ |
| 19 | #define NXP_QSPI_FLASH_ADDR 0x20000000 |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 20 | |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 21 | /* IFC Region #1 base address */ |
| 22 | #define NXP_NOR_FLASH_ADDR 0x30000000 |
| 23 | |
| 24 | /* MMU 500 */ |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 25 | #define NXP_SMMU_ADDR 0x05000000 |
| 26 | |
| 27 | #define NXP_SNVS_ADDR 0x01E90000 |
| 28 | |
| 29 | #define NXP_DCFG_ADDR 0x01E00000 |
| 30 | #define NXP_PMU_CCSR_ADDR 0x01E30000 |
| 31 | #define NXP_PMU_DCSR_ADDR 0x700123000 |
| 32 | #define NXP_PMU_ADDR NXP_PMU_CCSR_ADDR |
| 33 | #define NXP_SFP_ADDR 0x01E80000 |
| 34 | #define NXP_SCFG_ADDR 0x01FC0000 |
| 35 | #define NXP_I2C_ADDR 0x02000000 |
| 36 | #define NXP_ESDHC_ADDR 0x02140000 |
| 37 | #define NXP_ESDHC2_ADDR 0x02150000 |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 38 | #ifndef NXP_UART_ADDR |
| 39 | #define NXP_UART_ADDR 0x021C0500 |
| 40 | #endif |
| 41 | #ifndef NXP_UART1_ADDR |
| 42 | #define NXP_UART1_ADDR 0x021C0600 |
| 43 | #endif |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 44 | |
| 45 | #define NXP_GPIO1_ADDR 0x02300000 |
| 46 | #define NXP_GPIO2_ADDR 0x02310000 |
| 47 | #define NXP_GPIO3_ADDR 0x02320000 |
| 48 | #define NXP_GPIO4_ADDR 0x02330000 |
| 49 | |
| 50 | #define NXP_WDOG1_NS_ADDR 0x02390000 |
| 51 | #define NXP_WDOG2_NS_ADDR 0x023A0000 |
| 52 | #define NXP_WDOG1_TZ_ADDR 0x023B0000 |
| 53 | #define NXP_WDOG2_TZ_ADDR 0x023C0000 |
| 54 | |
| 55 | #define NXP_TIMER_STATUS_ADDR 0x023F0000 |
| 56 | |
| 57 | #define NXP_GICD_ADDR 0x06000000 |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 58 | #define NXP_GICR_ADDR 0x06100000 |
| 59 | #define NXP_GICR_SGI_ADDR 0x06110000 |
Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 60 | |
| 61 | #define NXP_CAAM_ADDR 0x08000000 |
| 62 | |
| 63 | #define NXP_TZC_ADDR 0x01100000 |
| 64 | #define NXP_TZC2_ADDR 0x01110000 |
| 65 | #define NXP_TZC3_ADDR 0x01120000 |
| 66 | |
| 67 | #define NXP_RESET_ADDR 0x01E60000 |
| 68 | #define NXP_SEC_REGFILE_ADDR 0x01E88000 |
Jiafei Pan | 21a3284 | 2022-02-18 15:24:27 +0800 | [diff] [blame] | 69 | |
| 70 | #define NXP_RST_ADDR 0x01E88000 |
| 71 | |
| 72 | /* DDR memory Map */ |
| 73 | #define NXP_DDR_ADDR 0x01080000 |
| 74 | #define NXP_DDR2_ADDR 0x01090000 |
| 75 | #define NXP_DDR3_ADDR 0x08210000 |
| 76 | |
| 77 | /* QuadSPI base address */ |
| 78 | #define NXP_QSPI_ADDR 0x020C0000 |
| 79 | /* IFC base address */ |
| 80 | #define NXP_IFC_ADDR 0x02240000 |
| 81 | |
| 82 | /* CCI400 base address */ |
| 83 | #define NXP_CCI_ADDR 0x04090000 |
| 84 | |
| 85 | /* Global Generic Reference Timer base address */ |
| 86 | #define NXP_TIMER_ADDR 0x023E0000 |
| 87 | |
| 88 | /* OCRAM TZPC base address */ |
| 89 | #define NXP_OCRAM_TZPC_ADDR 0x02200000 |
| 90 | |
| 91 | #define NXP_EPU_ADDR 0x700060000 |
| 92 | |
| 93 | #define NXP_CCN_ADDR 0x04000000 |
| 94 | #define NXP_CCN_HNI_ADDR 0x04080000 |
| 95 | #define NXP_CCN_HN_F_0_ADDR 0x04200000 |
| 96 | #define NXP_CCN_HN_F_1_ADDR 0x04210000 |
| 97 | |
| 98 | #define TPMWAKEMR0_ADDR 0x700123c50 |
| 99 | |
| 100 | #endif /* SOC_DEFAULT_BASE_ADDR_H */ |