Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | ab2d31e | 2013-12-02 19:25:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <assert.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include <console.h> |
| 36 | #include <platform.h> |
| 37 | #include <psci.h> |
| 38 | #include <psci_private.h> |
| 39 | |
| 40 | typedef int (*afflvl_off_handler)(unsigned long, aff_map_node *); |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * The next three functions implement a handler for each supported affinity |
| 44 | * level which is called when that affinity level is turned off. |
| 45 | ******************************************************************************/ |
| 46 | static int psci_afflvl0_off(unsigned long mpidr, aff_map_node *cpu_node) |
| 47 | { |
| 48 | unsigned int index, plat_state; |
| 49 | int rc = PSCI_E_SUCCESS; |
| 50 | unsigned long sctlr = read_sctlr(); |
| 51 | |
| 52 | assert(cpu_node->level == MPIDR_AFFLVL0); |
| 53 | |
| 54 | /* |
| 55 | * Generic management: Get the index for clearing any |
| 56 | * lingering re-entry information |
| 57 | */ |
| 58 | index = cpu_node->data; |
| 59 | memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index])); |
| 60 | |
| 61 | /* |
| 62 | * Arch. management. Perform the necessary steps to flush all |
| 63 | * cpu caches. |
| 64 | * |
| 65 | * TODO: This power down sequence varies across cpus so it needs to be |
| 66 | * abstracted out on the basis of the MIDR like in cpu_reset_handler(). |
| 67 | * Do the bare minimal for the time being. Fix this before porting to |
| 68 | * Cortex models. |
| 69 | */ |
| 70 | sctlr &= ~SCTLR_C_BIT; |
| 71 | write_sctlr(sctlr); |
| 72 | |
| 73 | /* |
| 74 | * CAUTION: This flush to the level of unification makes an assumption |
| 75 | * about the cache hierarchy at affinity level 0 (cpu) in the platform. |
| 76 | * Ideally the platform should tell psci which levels to flush to exit |
| 77 | * coherency. |
| 78 | */ |
| 79 | dcsw_op_louis(DCCISW); |
| 80 | |
| 81 | /* |
| 82 | * Plat. management: Perform platform specific actions to turn this |
| 83 | * cpu off e.g. exit cpu coherency, program the power controller etc. |
| 84 | */ |
| 85 | if (psci_plat_pm_ops->affinst_off) { |
| 86 | |
| 87 | /* Get the current physical state of this cpu */ |
| 88 | plat_state = psci_get_aff_phys_state(cpu_node); |
| 89 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 90 | cpu_node->level, |
| 91 | plat_state); |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * The only error cpu_off can return is E_DENIED. So check if that's |
| 96 | * indeed the case. The caller will simply 'eret' in case of an error. |
| 97 | */ |
| 98 | if (rc != PSCI_E_SUCCESS) |
| 99 | assert(rc == PSCI_E_DENIED); |
| 100 | |
| 101 | return rc; |
| 102 | } |
| 103 | |
| 104 | static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node) |
| 105 | { |
| 106 | int rc = PSCI_E_SUCCESS; |
| 107 | unsigned int plat_state; |
| 108 | |
| 109 | /* Sanity check the cluster level */ |
| 110 | assert(cluster_node->level == MPIDR_AFFLVL1); |
| 111 | |
| 112 | /* |
| 113 | * Keep the physical state of this cluster handy to decide |
| 114 | * what action needs to be taken |
| 115 | */ |
| 116 | plat_state = psci_get_aff_phys_state(cluster_node); |
| 117 | |
| 118 | /* |
| 119 | * Arch. Management. Flush all levels of caches to PoC if |
| 120 | * the cluster is to be shutdown |
| 121 | */ |
| 122 | if (plat_state == PSCI_STATE_OFF) |
| 123 | dcsw_op_all(DCCISW); |
| 124 | |
| 125 | /* |
| 126 | * Plat. Management. Allow the platform to do it's cluster |
| 127 | * specific bookeeping e.g. turn off interconnect coherency, |
| 128 | * program the power controller etc. |
| 129 | */ |
| 130 | if (psci_plat_pm_ops->affinst_off) |
| 131 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 132 | cluster_node->level, |
| 133 | plat_state); |
| 134 | |
| 135 | return rc; |
| 136 | } |
| 137 | |
| 138 | static int psci_afflvl2_off(unsigned long mpidr, aff_map_node *system_node) |
| 139 | { |
| 140 | int rc = PSCI_E_SUCCESS; |
| 141 | unsigned int plat_state; |
| 142 | |
| 143 | /* Cannot go beyond this level */ |
| 144 | assert(system_node->level == MPIDR_AFFLVL2); |
| 145 | |
| 146 | /* |
| 147 | * Keep the physical state of the system handy to decide what |
| 148 | * action needs to be taken |
| 149 | */ |
| 150 | plat_state = psci_get_aff_phys_state(system_node); |
| 151 | |
| 152 | /* No arch. and generic bookeeping to do here currently */ |
| 153 | |
| 154 | /* |
| 155 | * Plat. Management : Allow the platform to do it's bookeeping |
| 156 | * at this affinity level |
| 157 | */ |
| 158 | if (psci_plat_pm_ops->affinst_off) |
| 159 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 160 | system_node->level, |
| 161 | plat_state); |
| 162 | return rc; |
| 163 | } |
| 164 | |
| 165 | static const afflvl_off_handler psci_afflvl_off_handlers[] = { |
| 166 | psci_afflvl0_off, |
| 167 | psci_afflvl1_off, |
| 168 | psci_afflvl2_off, |
| 169 | }; |
| 170 | |
| 171 | /******************************************************************************* |
| 172 | * This function implements the core of the processing required to turn a cpu |
| 173 | * off. It's assumed that along with turning the cpu off, higher affinity levels |
| 174 | * will be turned off as far as possible. We first need to determine the new |
| 175 | * state off all the affinity instances in the mpidr corresponding to the target |
| 176 | * cpu. Action will be taken on the basis of this new state. To do the state |
| 177 | * change we first need to acquire the locks for all the implemented affinity |
| 178 | * level to be able to snapshot the system state. Then we need to start turning |
| 179 | * affinity levels off from the lowest to the highest (e.g. a cpu needs to be |
| 180 | * off before a cluster can be turned off). To achieve this flow, we start |
| 181 | * acquiring the locks from the highest to the lowest affinity level. Once we |
| 182 | * reach affinity level 0, we do the state change followed by the actions |
| 183 | * corresponding to the new state for affinity level 0. Actions as per the |
| 184 | * updated state for higher affinity levels are performed as we unwind back to |
| 185 | * highest affinity level. |
| 186 | ******************************************************************************/ |
| 187 | int psci_afflvl_off(unsigned long mpidr, |
| 188 | int cur_afflvl, |
| 189 | int tgt_afflvl) |
| 190 | { |
| 191 | int rc = PSCI_E_SUCCESS, level; |
| 192 | unsigned int next_state, prev_state; |
| 193 | aff_map_node *aff_node; |
| 194 | |
| 195 | mpidr &= MPIDR_AFFINITY_MASK;; |
| 196 | |
| 197 | /* |
| 198 | * Some affinity instances at levels between the current and |
| 199 | * target levels could be absent in the mpidr. Skip them and |
| 200 | * start from the first present instance. |
| 201 | */ |
| 202 | level = psci_get_first_present_afflvl(mpidr, |
| 203 | cur_afflvl, |
| 204 | tgt_afflvl, |
| 205 | &aff_node); |
| 206 | /* |
| 207 | * Return if there are no more affinity instances beyond this |
| 208 | * level to process. Else ensure that the returned affinity |
| 209 | * node makes sense. |
| 210 | */ |
| 211 | if (aff_node == NULL) |
| 212 | return rc; |
| 213 | |
| 214 | assert(level == aff_node->level); |
| 215 | |
| 216 | /* |
| 217 | * This function acquires the lock corresponding to each |
| 218 | * affinity level so that state management can be done safely. |
| 219 | */ |
| 220 | bakery_lock_get(mpidr, &aff_node->lock); |
| 221 | |
| 222 | /* Keep the old state and the next one handy */ |
| 223 | prev_state = psci_get_state(aff_node->state); |
| 224 | next_state = PSCI_STATE_OFF; |
| 225 | |
| 226 | /* |
| 227 | * We start from the highest affinity level and work our way |
| 228 | * downwards to the lowest i.e. MPIDR_AFFLVL0. |
| 229 | */ |
| 230 | if (aff_node->level == tgt_afflvl) { |
| 231 | psci_change_state(mpidr, |
| 232 | tgt_afflvl, |
| 233 | get_max_afflvl(), |
| 234 | next_state); |
| 235 | } else { |
| 236 | rc = psci_afflvl_off(mpidr, level - 1, tgt_afflvl); |
| 237 | if (rc != PSCI_E_SUCCESS) { |
| 238 | psci_set_state(aff_node->state, prev_state); |
| 239 | goto exit; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | /* |
| 244 | * Perform generic, architecture and platform specific |
| 245 | * handling |
| 246 | */ |
| 247 | rc = psci_afflvl_off_handlers[level](mpidr, aff_node); |
| 248 | if (rc != PSCI_E_SUCCESS) { |
| 249 | psci_set_state(aff_node->state, prev_state); |
| 250 | goto exit; |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * If all has gone as per plan then this cpu should be |
| 255 | * marked as OFF |
| 256 | */ |
| 257 | if (level == MPIDR_AFFLVL0) { |
| 258 | next_state = psci_get_state(aff_node->state); |
| 259 | assert(next_state == PSCI_STATE_OFF); |
| 260 | } |
| 261 | |
| 262 | exit: |
| 263 | bakery_lock_release(mpidr, &aff_node->lock); |
| 264 | return rc; |
| 265 | } |