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Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +08001/*
2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_FCS_H
8#define SOCFPGA_FCS_H
9
10/* FCS Definitions */
11
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080012#define FCS_RANDOM_WORD_SIZE 8U
13#define FCS_PROV_DATA_WORD_SIZE 44U
14#define FCS_SHA384_WORD_SIZE 12U
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080015
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080016#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
17#define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U
18#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
19#define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U)
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080020
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080021#define FCS_RANDOM_EXT_OFFSET 3
Sieu Mun Tange7a037f2022-05-10 17:18:19 +080022
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080023#define FCS_MODE_DECRYPT 0x0
24#define FCS_MODE_ENCRYPT 0x1
25#define FCS_ENCRYPTION_DATA_0 0x10100
26#define FCS_DECRYPTION_DATA_0 0x10102
27#define FCS_OWNER_ID_OFFSET 0xC
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080028
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080029#define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4
30#define PSGSIGMA_SESSION_ID_ONE 0x1
31#define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF
Sieu Mun Tang2a820b92022-05-11 09:59:55 +080032
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080033#define RESERVED_AS_ZERO 0x0
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +080034/* FCS Single cert */
35
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080036#define FCS_BIG_CNTR_SEL 0x1
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +080037
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080038#define FCS_SVN_CNTR_0_SEL 0x2
39#define FCS_SVN_CNTR_1_SEL 0x3
40#define FCS_SVN_CNTR_2_SEL 0x4
41#define FCS_SVN_CNTR_3_SEL 0x5
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +080042
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080043#define FCS_BIG_CNTR_VAL_MAX 495U
44#define FCS_SVN_CNTR_VAL_MAX 64U
Sieu Mun Tang2a820b92022-05-11 09:59:55 +080045
Sieu Mun Tang28af1652022-05-09 10:48:53 +080046/* FCS Attestation Cert Request Parameter */
47
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080048#define FCS_ALIAS_CERT 0x01
49#define FCS_DEV_ID_SELF_SIGN_CERT 0x02
50#define FCS_DEV_ID_ENROLL_CERT 0x04
51#define FCS_ENROLL_SELF_SIGN_CERT 0x08
52#define FCS_PLAT_KEY_CERT 0x10
Sieu Mun Tang28af1652022-05-09 10:48:53 +080053
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +080054/* FCS Crypto Service */
55
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080056#define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U
57#define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U
58#define FCS_CS_KEY_RESP_STATUS_MASK 0xFF
59#define FCS_CS_KEY_RESP_STATUS_OFFSET 16U
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +080060
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080061#define FCS_CS_FIELD_SIZE_MASK 0xFFFF
62#define FCS_CS_FIELD_FLAG_OFFSET 24
63#define FCS_CS_FIELD_FLAG_INIT BIT(0)
64#define FCS_CS_FIELD_FLAG_UPDATE BIT(1)
65#define FCS_CS_FIELD_FLAG_FINALIZE BIT(2)
Sieu Mun Tange7a037f2022-05-10 17:18:19 +080066
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080067#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
68#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
Sieu Mun Tang583149a2022-05-10 17:27:12 +080069#define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
70#define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U
Sieu Mun Tangd907cc32022-05-10 17:24:05 +080071#define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080072/* FCS Payload Structure */
Sieu Mun Tange7a037f2022-05-10 17:18:19 +080073typedef struct fcs_rng_payload_t {
74 uint32_t session_id;
75 uint32_t context_id;
76 uint32_t crypto_header;
77 uint32_t size;
78} fcs_rng_payload;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080079
Sieu Mun Tang128d2a72022-05-11 09:49:25 +080080typedef struct fcs_encrypt_payload_t {
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080081 uint32_t first_word;
82 uint32_t src_addr;
83 uint32_t src_size;
84 uint32_t dst_addr;
85 uint32_t dst_size;
Sieu Mun Tang128d2a72022-05-11 09:49:25 +080086} fcs_encrypt_payload;
87
88typedef struct fcs_decrypt_payload_t {
89 uint32_t first_word;
90 uint32_t owner_id[2];
91 uint32_t src_addr;
92 uint32_t src_size;
93 uint32_t dst_addr;
94 uint32_t dst_size;
95} fcs_decrypt_payload;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080096
Sieu Mun Tang2a820b92022-05-11 09:59:55 +080097typedef struct psgsigma_teardown_msg_t {
98 uint32_t reserved_word;
99 uint32_t magic_word;
100 uint32_t session_id;
101} psgsigma_teardown_msg;
102
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +0800103typedef struct fcs_cntr_set_preauth_payload_t {
104 uint32_t first_word;
105 uint32_t counter_value;
106} fcs_cntr_set_preauth_payload;
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800107
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +0800108typedef struct fcs_cs_key_payload_t {
109 uint32_t session_id;
110 uint32_t reserved0;
111 uint32_t reserved1;
112 uint32_t key_id;
113} fcs_cs_key_payload;
114
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800115typedef struct fcs_crypto_service_data_t {
116 uint32_t session_id;
117 uint32_t context_id;
118 uint32_t key_id;
119 uint32_t crypto_param_size;
120 uint64_t crypto_param;
121} fcs_crypto_service_data;
122
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800123/* Functions Definitions */
124
125uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
126 uint32_t *mbox_error);
Sieu Mun Tange7a037f2022-05-10 17:18:19 +0800127int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
128 uint32_t size, uint32_t *send_id);
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800129uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
130 uint32_t *send_id);
131uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +0800132uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
133 int32_t counter_value,
134 uint32_t test_bit,
135 uint32_t *mbox_error);
Sieu Mun Tang128d2a72022-05-11 09:49:25 +0800136uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
137 uint32_t dst_addr, uint32_t dst_size,
138 uint32_t *send_id);
139
140uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
141 uint32_t dst_addr, uint32_t dst_size,
142 uint32_t *send_id);
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800143
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800144int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
145int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
146int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size,
147 uint64_t dst_addr, uint32_t *dst_size,
148 uint32_t *mbox_error);
149int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
150 uint64_t dst_addr, uint32_t *dst_size,
151 uint32_t *mbox_error);
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800152uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
153 uint32_t *mbox_error);
154
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800155int intel_fcs_create_cert_on_reload(uint32_t cert_request,
156 uint32_t *mbox_error);
157int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
158 uint32_t *dst_size, uint32_t *mbox_error);
159
Sieu Mun Tang16754e12022-05-09 12:08:42 +0800160int intel_fcs_open_crypto_service_session(uint32_t *session_id,
161 uint32_t *mbox_error);
162int intel_fcs_close_crypto_service_session(uint32_t session_id,
163 uint32_t *mbox_error);
164
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +0800165int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size,
166 uint32_t *mbox_error);
167int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id,
168 uint64_t dst_addr, uint32_t *dst_size,
169 uint32_t *mbox_error);
170int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id,
171 uint32_t *mbox_error);
172int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id,
173 uint64_t dst_addr, uint32_t *dst_size,
174 uint32_t *mbox_error);
175
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800176int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
177 uint32_t key_id, uint32_t param_size,
178 uint64_t param_data, uint32_t *mbox_error);
179int intel_fcs_get_digest_finalize(uint32_t session_id, uint32_t context_id,
180 uint32_t src_addr, uint32_t src_size,
181 uint64_t dst_addr, uint32_t *dst_size,
182 uint32_t *mbox_error);
183
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800184int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
185 uint32_t key_id, uint32_t param_size,
186 uint64_t param_data, uint32_t *mbox_error);
187int intel_fcs_mac_verify_finalize(uint32_t session_id, uint32_t context_id,
188 uint32_t src_addr, uint32_t src_size,
189 uint64_t dst_addr, uint32_t *dst_size,
190 uint32_t data_size, uint32_t *mbox_error);
191
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800192#endif /* SOCFPGA_FCS_H */