Sheetal Tigadoli | b015670 | 2020-01-05 14:59:04 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2016 - 2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CHAL_SD_H |
| 8 | #define CHAL_SD_H |
| 9 | |
| 10 | #include <stddef.h> |
| 11 | |
| 12 | #define BASE_CLK_FREQ (200 * 1000 * 1000) |
| 13 | #define INIT_CLK_FREQ (400 * 1000) |
| 14 | |
| 15 | #define SD_ERROR_RECOVERABLE 0 |
| 16 | #define SD_ERROR_NON_RECOVERABLE 1 |
| 17 | |
| 18 | #define SD_OK 0 |
| 19 | #define SD_FAIL (-1) |
| 20 | #define SD_INVALID_HANDLE (-2) |
| 21 | #define SD_CEATA_INIT_ERROR (-3) |
| 22 | #define SD_RESET_ERROR (-4) |
| 23 | #define SD_CARD_INIT_ERROR (-5) |
| 24 | #define SD_INV_DATA_WIDTH (-6) |
| 25 | #define SD_SET_BUS_WIDTH_ERROR (-7) |
| 26 | #define SD_DMA_NOT_SUPPORT (-8) |
| 27 | #define SD_SDIO_READ_ERROR (-9) |
| 28 | #define SD_SDIO_WRITE_ERROR (-10) |
| 29 | #define SD_WRITE_ERROR (-11) |
| 30 | #define SD_READ_ERROR (-12) |
| 31 | #define SD_READ_SIZE_ERROR (-13) |
| 32 | #define SD_RW_ADDRESS_ERROR (-14) |
| 33 | #define SD_XFER_ADDRESS_ERROR (-15) |
| 34 | #define SD_DATA_XFER_ADDR_ERROR (-16) |
| 35 | #define SD_DATA_XFER_ERROR (-17) |
| 36 | #define SD_WRITE_SIZE_ERROR (-18) |
| 37 | #define SD_CMD_STATUS_UPDATE_ERR (-19) |
| 38 | #define SD_CMD12_ERROR (-20) |
| 39 | #define SD_CMD_DATA_ERROR (-21) |
| 40 | #define SD_CMD_TIMEOUT (-22) |
| 41 | #define SD_CMD_NO_RESPONSE (-22) |
| 42 | #define SD_CMD_ABORT_ERROR (-23) |
| 43 | #define SD_CMD_INVALID (-24) |
| 44 | #define SD_CMD_RESUME_ERROR (-25) |
| 45 | #define SD_CMD_ERR_INVALID_RESPONSE (-26) |
| 46 | #define SD_WAIT_TIMEOUT (-27) |
| 47 | #define SD_READ_TIMEOUT (-28) |
| 48 | #define SD_CEATA_REST_ERROR (-29) |
| 49 | #define SD_INIT_CAED_FAILED (-30) |
| 50 | #define SD_ERROR_CLOCK_OFFLIMIT (-31) |
| 51 | #define SD_INV_SLOT (-32) |
| 52 | |
| 53 | #define SD_NOR_INTERRUPTS 0x000000FF |
| 54 | #define SD_ERR_INTERRUPTS 0x03FF0000 |
| 55 | #define SD_CMD_ERROR_INT 0x010F0000 |
| 56 | #define SD_DAT_ERROR_INT 0x02F00000 |
| 57 | #define SD_DAT_TIMEOUT 0x00100000 |
| 58 | |
| 59 | /* Operation modes */ |
| 60 | #define SD_PIO_MODE 0 |
| 61 | #define SD_INT_MODE 1 |
| 62 | |
| 63 | /* Support both ADMA and SDMA (for version 2.0 and above) */ |
| 64 | #define SD_DMA_OFF 0 |
| 65 | #define SD_DMA_SDMA 1 |
| 66 | #define SD_DMA_ADMA 2 |
| 67 | |
| 68 | #define SD_NORMAL_SPEED 0 |
| 69 | #define SD_HIGH_SPEED 1 |
| 70 | |
| 71 | #define SD_XFER_CARD_TO_HOST 3 |
| 72 | #define SD_XFER_HOST_TO_CARD 4 |
| 73 | |
| 74 | #define SD_CARD_DETECT_AUTO 0 |
| 75 | #define SD_CARD_DETECT_SD 1 |
| 76 | #define SD_CARD_DETECT_SDIO 2 |
| 77 | #define SD_CARD_DETECT_MMC 3 |
| 78 | #define SD_CARD_DETECT_CEATA 4 |
| 79 | |
| 80 | #define SD_ABORT_SYNC_MODE 0 |
| 81 | #define SD_ABORT_ASYNC_MODE 1 |
| 82 | |
| 83 | #define SD_CMD_ERROR_FLAGS (0x18F << 16) |
| 84 | #define SD_DATA_ERROR_FLAGS (0x70 << 16) |
| 85 | #define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) |
| 86 | |
| 87 | #define SD_CARD_STATUS_ERROR 0x10000000 |
| 88 | #define SD_CMD_MISSING 0x80000000 |
| 89 | #define SD_ERROR_INT 0x8000 |
| 90 | |
| 91 | #define SD_TRAN_HIGH_SPEED 0x32 |
| 92 | #define SD_CARD_HIGH_CAPACITY 0x40000000 |
| 93 | #define SD_CARD_POWER_UP_STATUS 0x80000000 |
| 94 | |
| 95 | #define SD_HOST_CORE_TIMEOUT 0x0E |
| 96 | |
| 97 | /* SD CARD and Host Controllers bus width */ |
| 98 | #define SD_BUS_DATA_WIDTH_1BIT 0x00 |
| 99 | #define SD_BUS_DATA_WIDTH_4BIT 0x02 |
| 100 | #define SD_BUS_DATA_WIDTH_8BIT 0x20 |
| 101 | |
| 102 | /* dma boundary settings */ |
| 103 | #define SD_DMA_BOUNDARY_4K 0 |
| 104 | #define SD_DMA_BOUNDARY_8K (1 << 12) |
| 105 | #define SD_DMA_BOUNDARY_16K (2 << 12) |
| 106 | #define SD_DMA_BOUNDARY_32K (3 << 12) |
| 107 | #define SD_DMA_BOUNDARY_64K (4 << 12) |
| 108 | #define SD_DMA_BOUNDARY_128K (5 << 12) |
| 109 | #define SD_DMA_BOUNDARY_256K (6 << 12) |
| 110 | #define SD_DMA_BOUNDARY_512K (7 << 12) |
| 111 | |
| 112 | #define SD_CMDR_CMD_NORMAL 0x00000000 |
| 113 | #define SD_CMDR_CMD_SUSPEND 0x00400000 |
| 114 | #define SD_CMDR_CMD_RESUME 0x00800000 |
| 115 | #define SD_CMDR_CMD_ABORT 0x00c00000 |
| 116 | |
| 117 | #define SD_CMDR_RSP_TYPE_NONE 0x0 |
| 118 | #define SD_CMDR_RSP_TYPE_R2 0x1 |
| 119 | #define SD_CMDR_RSP_TYPE_R3_4 0x2 |
| 120 | #define SD_CMDR_RSP_TYPE_R1_5_6 0x2 |
| 121 | #define SD_CMDR_RSP_TYPE_R1b_5b 0x3 |
| 122 | #define SD_CMDR_RSP_TYPE_S 16 |
| 123 | |
| 124 | struct sd_ctrl_info { |
| 125 | uint32_t blkReg; /* current block register cache value */ |
| 126 | uint32_t cmdReg; /* current command register cache value */ |
| 127 | uint32_t argReg; /* current argument register cache value */ |
| 128 | uint32_t cmdIndex; /* current command index */ |
| 129 | uint32_t cmdStatus; /* current command status, cmd/data compelete */ |
| 130 | uint16_t rca; /* relative card address */ |
| 131 | uint32_t ocr; /* operation codition */ |
| 132 | uint32_t eventList; /* events list */ |
| 133 | uint32_t blkGapEnable; |
| 134 | |
| 135 | uint32_t capability; /* controller's capbilities */ |
| 136 | uint32_t maxCurrent; /* maximum current supported */ |
| 137 | uint32_t present; /* if card is inserted or removed */ |
| 138 | uint32_t version; /* SD spec version 1.0 or 2.0 */ |
| 139 | uint32_t vendor; /* vendor number */ |
| 140 | |
| 141 | uintptr_t sdRegBaseAddr; /* sdio control registers */ |
| 142 | uintptr_t hostRegBaseAddr; /* SD Host control registers */ |
| 143 | }; |
| 144 | |
| 145 | struct sd_cfg { |
| 146 | uint32_t mode; /* interrupt or polling */ |
| 147 | uint32_t dma; /* dma enabled or disabled */ |
| 148 | uint32_t retryLimit; /* command retry limit */ |
| 149 | uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */ |
| 150 | uint32_t voltage; /* voltage level */ |
| 151 | uint32_t blockSize; /* access block size (512 for HC card) */ |
| 152 | uint32_t dmaBoundary; /* dma address boundary */ |
| 153 | uint32_t detSignal; /* card det signal src, for test purpose only */ |
| 154 | uint32_t rdWaiting; |
| 155 | uint32_t wakeupOut; |
| 156 | uint32_t wakeupIn; |
| 157 | uint32_t wakeupInt; |
| 158 | uint32_t wfe_retry; |
| 159 | uint32_t gapInt; |
| 160 | uint32_t readWait; |
| 161 | uint32_t led; |
| 162 | }; |
| 163 | |
| 164 | struct sd_dev { |
| 165 | struct sd_cfg cfg; /* SD configuration */ |
| 166 | struct sd_ctrl_info ctrl; /* SD info */ |
| 167 | }; |
| 168 | |
| 169 | int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode, |
| 170 | uint32_t sdBase, uint32_t hostBase); |
| 171 | int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed, |
| 172 | uint32_t retry, uint32_t boundary, |
| 173 | uint32_t blkSize, uint32_t dma); |
| 174 | int32_t chal_sd_stop(void); |
| 175 | int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode); |
| 176 | uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle); |
| 177 | int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width); |
| 178 | int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex, |
| 179 | uint32_t arg, uint32_t options); |
| 180 | int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address); |
| 181 | int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle, |
| 182 | uint32_t div_ctrl_setting, uint32_t on); |
| 183 | uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq); |
| 184 | int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data, |
| 185 | uint32_t length, int32_t dir); |
| 186 | int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length, |
| 187 | uint8_t *data); |
| 188 | int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length, |
| 189 | uint8_t *data); |
| 190 | int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line); |
| 191 | int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp); |
| 192 | int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle); |
| 193 | int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle); |
| 194 | int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask); |
| 195 | uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle); |
| 196 | int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle); |
| 197 | void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed); |
| 198 | int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap); |
| 199 | void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask, |
| 200 | uint32_t state); |
| 201 | void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle); |
| 202 | #endif /* CHAL_SD_H */ |