Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved |
Yann Gautier | e753470 | 2019-02-14 11:14:18 +0100 | [diff] [blame] | 3 | * Copyright (c) 2018-2019, Linaro Limited |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef STM32MP_COMMON_H |
| 9 | #define STM32MP_COMMON_H |
| 10 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 11 | #include <stdbool.h> |
| 12 | |
Yann Gautier | e753470 | 2019-02-14 11:14:18 +0100 | [diff] [blame] | 13 | #include <arch_helpers.h> |
| 14 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 15 | /* Functions to save and get boot context address given by ROM code */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 16 | void stm32mp_save_boot_ctx_address(uintptr_t address); |
| 17 | uintptr_t stm32mp_get_boot_ctx_address(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 18 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 19 | /* Return the base address of the DDR controller */ |
| 20 | uintptr_t stm32mp_ddrctrl_base(void); |
| 21 | |
| 22 | /* Return the base address of the DDR PHY */ |
| 23 | uintptr_t stm32mp_ddrphyc_base(void); |
| 24 | |
| 25 | /* Return the base address of the PWR peripheral */ |
| 26 | uintptr_t stm32mp_pwr_base(void); |
| 27 | |
| 28 | /* Return the base address of the RCC peripheral */ |
| 29 | uintptr_t stm32mp_rcc_base(void); |
| 30 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 31 | /* |
| 32 | * Platform util functions for the GPIO driver |
| 33 | * @bank: Target GPIO bank ID as per DT bindings |
| 34 | * |
| 35 | * Platform shall implement these functions to provide to stm32_gpio |
| 36 | * driver the resource reference for a target GPIO bank. That are |
| 37 | * memory mapped interface base address, interface offset (see below) |
| 38 | * and clock identifier. |
| 39 | * |
| 40 | * stm32_get_gpio_bank_offset() returns a bank offset that is used to |
| 41 | * check DT configuration matches platform implementation of the banks |
| 42 | * description. |
| 43 | */ |
| 44 | uintptr_t stm32_get_gpio_bank_base(unsigned int bank); |
| 45 | unsigned long stm32_get_gpio_bank_clock(unsigned int bank); |
| 46 | uint32_t stm32_get_gpio_bank_offset(unsigned int bank); |
| 47 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 48 | /* |
| 49 | * Util for clock gating and to get clock rate for stm32 and platform drivers |
| 50 | * @id: Target clock ID, ID used in clock DT bindings |
| 51 | */ |
| 52 | bool stm32mp_clk_is_enabled(unsigned long id); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 53 | void stm32mp_clk_enable(unsigned long id); |
| 54 | void stm32mp_clk_disable(unsigned long id); |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 55 | unsigned long stm32mp_clk_get_rate(unsigned long id); |
| 56 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 57 | /* Initialise the IO layer and register platform IO devices */ |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 58 | void stm32mp_io_setup(void); |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 59 | |
Yann Gautier | e753470 | 2019-02-14 11:14:18 +0100 | [diff] [blame] | 60 | static inline uint64_t arm_cnt_us2cnt(uint32_t us) |
| 61 | { |
| 62 | return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL; |
| 63 | } |
| 64 | |
| 65 | static inline uint64_t timeout_init_us(uint32_t us) |
| 66 | { |
| 67 | return read_cntpct_el0() + arm_cnt_us2cnt(us); |
| 68 | } |
| 69 | |
| 70 | static inline bool timeout_elapsed(uint64_t expire) |
| 71 | { |
| 72 | return read_cntpct_el0() > expire; |
| 73 | } |
| 74 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 75 | #endif /* STM32MP_COMMON_H */ |