Blame - lib/arch/aarch64/sysreg_helpers.S - filogic/atf

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Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	1	/*
Dan Handley	e83b0ca	2014-01-14 18:17:09 +0000	[diff] [blame]	2	* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	3	*
				4	* Redistribution and use in source and binary forms, with or without
				5	* modification, are permitted provided that the following conditions are met:
				6	*
				7	* Redistributions of source code must retain the above copyright notice, this
				8	* list of conditions and the following disclaimer.
				9	*
				10	* Redistributions in binary form must reproduce the above copyright notice,
				11	* this list of conditions and the following disclaimer in the documentation
				12	* and/or other materials provided with the distribution.
				13	*
				14	* Neither the name of ARM nor the names of its contributors may be used
				15	* to endorse or promote products derived from this software without specific
				16	* prior written permission.
				17	*
				18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
				19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
				20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
				21	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
				22	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
				23	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
				24	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
				25	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
				26	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
				27	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
				28	* POSSIBILITY OF SUCH DAMAGE.
				29	*/
				30
				31	#include <arch_helpers.h>
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	32	#include <asm_macros.S>
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	33
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	34	.globl read_vbar_el1
				35	.globl read_vbar_el2
				36	.globl read_vbar_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	37	.globl write_vbar_el1
				38	.globl write_vbar_el2
				39	.globl write_vbar_el3
				40
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	41	.globl read_sctlr_el1
				42	.globl read_sctlr_el2
				43	.globl read_sctlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	44	.globl write_sctlr_el1
				45	.globl write_sctlr_el2
				46	.globl write_sctlr_el3
				47
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	48	.globl read_actlr_el1
				49	.globl read_actlr_el2
				50	.globl read_actlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	51	.globl write_actlr_el1
				52	.globl write_actlr_el2
				53	.globl write_actlr_el3
				54
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	55	.globl read_esr_el1
				56	.globl read_esr_el2
				57	.globl read_esr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	58	.globl write_esr_el1
				59	.globl write_esr_el2
				60	.globl write_esr_el3
				61
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	62	.globl read_afsr0_el1
				63	.globl read_afsr0_el2
				64	.globl read_afsr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	65	.globl write_afsr0_el1
				66	.globl write_afsr0_el2
				67	.globl write_afsr0_el3
				68
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	69	.globl read_afsr1_el1
				70	.globl read_afsr1_el2
				71	.globl read_afsr1_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	72	.globl write_afsr1_el1
				73	.globl write_afsr1_el2
				74	.globl write_afsr1_el3
				75
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	76	.globl read_far_el1
				77	.globl read_far_el2
				78	.globl read_far_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	79	.globl write_far_el1
				80	.globl write_far_el2
				81	.globl write_far_el3
				82
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	83	.globl read_mair_el1
				84	.globl read_mair_el2
				85	.globl read_mair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	86	.globl write_mair_el1
				87	.globl write_mair_el2
				88	.globl write_mair_el3
				89
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	90	.globl read_amair_el1
				91	.globl read_amair_el2
				92	.globl read_amair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	93	.globl write_amair_el1
				94	.globl write_amair_el2
				95	.globl write_amair_el3
				96
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	97	.globl read_rvbar_el1
				98	.globl read_rvbar_el2
				99	.globl read_rvbar_el3
				100
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	101	.globl read_rmr_el1
				102	.globl read_rmr_el2
				103	.globl read_rmr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	104	.globl write_rmr_el1
				105	.globl write_rmr_el2
				106	.globl write_rmr_el3
				107
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	108	.globl read_tcr_el1
				109	.globl read_tcr_el2
				110	.globl read_tcr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	111	.globl write_tcr_el1
				112	.globl write_tcr_el2
				113	.globl write_tcr_el3
				114
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	115	.globl read_cptr_el2
				116	.globl read_cptr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	117	.globl write_cptr_el2
				118	.globl write_cptr_el3
				119
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	120	.globl read_ttbr0_el1
				121	.globl read_ttbr0_el2
				122	.globl read_ttbr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	123	.globl write_ttbr0_el1
				124	.globl write_ttbr0_el2
				125	.globl write_ttbr0_el3
				126
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	127	.globl read_ttbr1_el1
				128	.globl read_ttbr1_el2
				129	.globl write_ttbr1
				130	.globl write_ttbr1_el1
				131	.globl write_ttbr1_el2
				132
				133	.globl read_cpacr
				134	.globl write_cpacr
				135
				136	.globl read_cntfrq
				137	.globl write_cntfrq
				138
				139	.globl read_cpuectlr
				140	.globl write_cpuectlr
				141
				142	.globl read_cnthctl_el2
				143	.globl write_cnthctl_el2
				144
				145	.globl read_cntfrq_el0
				146	.globl write_cntfrq_el0
				147
				148	.globl read_scr
				149	.globl write_scr
				150
				151	.globl read_hcr
				152	.globl write_hcr
				153
				154	.globl read_midr
				155	.globl read_mpidr
				156
				157	.globl read_current_el
				158	.globl read_id_pfr1_el1
				159	.globl read_id_aa64pfr0_el1
				160
				161	#if SUPPORT_VFP
				162	.globl enable_vfp
				163	.globl read_fpexc
				164	.globl write_fpexc
				165	#endif
				166
				167
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	168	func read_current_el
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	169	mrs x0, CurrentEl
				170	ret
				171
				172
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	173	func read_id_pfr1_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	174	mrs x0, id_pfr1_el1
				175	ret
				176
				177
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	178	func read_id_aa64pfr0_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	179	mrs x0, id_aa64pfr0_el1
				180	ret
				181
				182
				183	/* -----------------------------------------------------
				184	* VBAR accessors
				185	* -----------------------------------------------------
				186	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	187	func read_vbar_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	188	mrs x0, vbar_el1
				189	ret
				190
				191
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	192	func read_vbar_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	193	mrs x0, vbar_el2
				194	ret
				195
				196
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	197	func read_vbar_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	198	mrs x0, vbar_el3
				199	ret
				200
				201
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	202	func write_vbar_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	203	msr vbar_el1, x0
				204	isb
				205	ret
				206
				207
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	208	func write_vbar_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	209	msr vbar_el2, x0
				210	isb
				211	ret
				212
				213
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	214	func write_vbar_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	215	msr vbar_el3, x0
				216	isb
				217	ret
				218
				219
				220	/* -----------------------------------------------------
				221	* AFSR0 accessors
				222	* -----------------------------------------------------
				223	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	224	func read_afsr0_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	225	mrs x0, afsr0_el1
				226	ret
				227
				228
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	229	func read_afsr0_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	230	mrs x0, afsr0_el2
				231	ret
				232
				233
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	234	func read_afsr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	235	mrs x0, afsr0_el3
				236	ret
				237
				238
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	239	func write_afsr0_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	240	msr afsr0_el1, x0
				241	isb
				242	ret
				243
				244
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	245	func write_afsr0_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	246	msr afsr0_el2, x0
				247	isb
				248	ret
				249
				250
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	251	func write_afsr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	252	msr afsr0_el3, x0
				253	isb
				254	ret
				255
				256
				257	/* -----------------------------------------------------
				258	* FAR accessors
				259	* -----------------------------------------------------
				260	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	261	func read_far_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	262	mrs x0, far_el1
				263	ret
				264
				265
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	266	func read_far_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	267	mrs x0, far_el2
				268	ret
				269
				270
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	271	func read_far_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	272	mrs x0, far_el3
				273	ret
				274
				275
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	276	func write_far_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	277	msr far_el1, x0
				278	isb
				279	ret
				280
				281
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	282	func write_far_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	283	msr far_el2, x0
				284	isb
				285	ret
				286
				287
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	288	func write_far_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	289	msr far_el3, x0
				290	isb
				291	ret
				292
				293
				294	/* -----------------------------------------------------
				295	* MAIR accessors
				296	* -----------------------------------------------------
				297	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	298	func read_mair_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	299	mrs x0, mair_el1
				300	ret
				301
				302
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	303	func read_mair_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	304	mrs x0, mair_el2
				305	ret
				306
				307
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	308	func read_mair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	309	mrs x0, mair_el3
				310	ret
				311
				312
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	313	func write_mair_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	314	msr mair_el1, x0
				315	isb
				316	ret
				317
				318
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	319	func write_mair_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	320	msr mair_el2, x0
				321	isb
				322	ret
				323
				324
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	325	func write_mair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	326	msr mair_el3, x0
				327	isb
				328	ret
				329
				330
				331	/* -----------------------------------------------------
				332	* AMAIR accessors
				333	* -----------------------------------------------------
				334	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	335	func read_amair_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	336	mrs x0, amair_el1
				337	ret
				338
				339
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	340	func read_amair_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	341	mrs x0, amair_el2
				342	ret
				343
				344
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	345	func read_amair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	346	mrs x0, amair_el3
				347	ret
				348
				349
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	350	func write_amair_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	351	msr amair_el1, x0
				352	isb
				353	ret
				354
				355
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	356	func write_amair_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	357	msr amair_el2, x0
				358	isb
				359	ret
				360
				361
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	362	func write_amair_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	363	msr amair_el3, x0
				364	isb
				365	ret
				366
				367
				368	/* -----------------------------------------------------
				369	* RVBAR accessors
				370	* -----------------------------------------------------
				371	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	372	func read_rvbar_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	373	mrs x0, rvbar_el1
				374	ret
				375
				376
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	377	func read_rvbar_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	378	mrs x0, rvbar_el2
				379	ret
				380
				381
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	382	func read_rvbar_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	383	mrs x0, rvbar_el3
				384	ret
				385
				386
				387	/* -----------------------------------------------------
				388	* RMR accessors
				389	* -----------------------------------------------------
				390	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	391	func read_rmr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	392	mrs x0, rmr_el1
				393	ret
				394
				395
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	396	func read_rmr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	397	mrs x0, rmr_el2
				398	ret
				399
				400
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	401	func read_rmr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	402	mrs x0, rmr_el3
				403	ret
				404
				405
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	406	func write_rmr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	407	msr rmr_el1, x0
				408	isb
				409	ret
				410
				411
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	412	func write_rmr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	413	msr rmr_el2, x0
				414	isb
				415	ret
				416
				417
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	418	func write_rmr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	419	msr rmr_el3, x0
				420	isb
				421	ret
				422
				423
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	424	/* -----------------------------------------------------
				425	* AFSR1 accessors
				426	* -----------------------------------------------------
				427	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	428	func read_afsr1_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	429	mrs x0, afsr1_el1
				430	ret
				431
				432
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	433	func read_afsr1_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	434	mrs x0, afsr1_el2
				435	ret
				436
				437
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	438	func read_afsr1_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	439	mrs x0, afsr1_el3
				440	ret
				441
				442
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	443	func write_afsr1_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	444	msr afsr1_el1, x0
				445	isb
				446	ret
				447
				448
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	449	func write_afsr1_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	450	msr afsr1_el2, x0
				451	isb
				452	ret
				453
				454
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	455	func write_afsr1_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	456	msr afsr1_el3, x0
				457	isb
				458	ret
				459
				460
				461	/* -----------------------------------------------------
				462	* SCTLR accessors
				463	* -----------------------------------------------------
				464	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	465	func read_sctlr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	466	mrs x0, sctlr_el1
				467	ret
				468
				469
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	470	func read_sctlr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	471	mrs x0, sctlr_el2
				472	ret
				473
				474
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	475	func read_sctlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	476	mrs x0, sctlr_el3
				477	ret
				478
				479
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	480	func write_sctlr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	481	msr sctlr_el1, x0
				482	dsb sy
				483	isb
				484	ret
				485
				486
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	487	func write_sctlr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	488	msr sctlr_el2, x0
				489	dsb sy
				490	isb
				491	ret
				492
				493
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	494	func write_sctlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	495	msr sctlr_el3, x0
				496	dsb sy
				497	isb
				498	ret
				499
				500
				501	/* -----------------------------------------------------
				502	* ACTLR accessors
				503	* -----------------------------------------------------
				504	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	505	func read_actlr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	506	mrs x0, actlr_el1
				507	ret
				508
				509
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	510	func read_actlr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	511	mrs x0, actlr_el2
				512	ret
				513
				514
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	515	func read_actlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	516	mrs x0, actlr_el3
				517	ret
				518
				519
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	520	func write_actlr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	521	msr actlr_el1, x0
				522	dsb sy
				523	isb
				524	ret
				525
				526
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	527	func write_actlr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	528	msr actlr_el2, x0
				529	dsb sy
				530	isb
				531	ret
				532
				533
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	534	func write_actlr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	535	msr actlr_el3, x0
				536	dsb sy
				537	isb
				538	ret
				539
				540
				541	/* -----------------------------------------------------
				542	* ESR accessors
				543	* -----------------------------------------------------
				544	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	545	func read_esr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	546	mrs x0, esr_el1
				547	ret
				548
				549
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	550	func read_esr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	551	mrs x0, esr_el2
				552	ret
				553
				554
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	555	func read_esr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	556	mrs x0, esr_el3
				557	ret
				558
				559
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	560	func write_esr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	561	msr esr_el1, x0
				562	dsb sy
				563	isb
				564	ret
				565
				566
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	567	func write_esr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	568	msr esr_el2, x0
				569	dsb sy
				570	isb
				571	ret
				572
				573
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	574	func write_esr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	575	msr esr_el3, x0
				576	dsb sy
				577	isb
				578	ret
				579
				580
				581	/* -----------------------------------------------------
				582	* TCR accessors
				583	* -----------------------------------------------------
				584	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	585	func read_tcr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	586	mrs x0, tcr_el1
				587	ret
				588
				589
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	590	func read_tcr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	591	mrs x0, tcr_el2
				592	ret
				593
				594
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	595	func read_tcr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	596	mrs x0, tcr_el3
				597	ret
				598
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	599
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	600	func write_tcr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	601	msr tcr_el1, x0
				602	dsb sy
				603	isb
				604	ret
				605
				606
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	607	func write_tcr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	608	msr tcr_el2, x0
				609	dsb sy
				610	isb
				611	ret
				612
				613
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	614	func write_tcr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	615	msr tcr_el3, x0
				616	dsb sy
				617	isb
				618	ret
				619
				620
				621	/* -----------------------------------------------------
				622	* CPTR accessors
				623	* -----------------------------------------------------
				624	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	625	func read_cptr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	626	b read_cptr_el1
				627	ret
				628
				629
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	630	func read_cptr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	631	mrs x0, cptr_el2
				632	ret
				633
				634
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	635	func read_cptr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	636	mrs x0, cptr_el3
				637	ret
				638
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	639
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	640	func write_cptr_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	641	b write_cptr_el1
				642
				643
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	644	func write_cptr_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	645	msr cptr_el2, x0
				646	dsb sy
				647	isb
				648	ret
				649
				650
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	651	func write_cptr_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	652	msr cptr_el3, x0
				653	dsb sy
				654	isb
				655	ret
				656
				657
				658	/* -----------------------------------------------------
				659	* TTBR0 accessors
				660	* -----------------------------------------------------
				661	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	662	func read_ttbr0_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	663	mrs x0, ttbr0_el1
				664	ret
				665
				666
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	667	func read_ttbr0_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	668	mrs x0, ttbr0_el2
				669	ret
				670
				671
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	672	func read_ttbr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	673	mrs x0, ttbr0_el3
				674	ret
				675
				676
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	677	func write_ttbr0_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	678	msr ttbr0_el1, x0
				679	isb
				680	ret
				681
				682
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	683	func write_ttbr0_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	684	msr ttbr0_el2, x0
				685	isb
				686	ret
				687
				688
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	689	func write_ttbr0_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	690	msr ttbr0_el3, x0
				691	isb
				692	ret
				693
				694
				695	/* -----------------------------------------------------
				696	* TTBR1 accessors
				697	* -----------------------------------------------------
				698	*/
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	699	func read_ttbr1_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	700	mrs x0, ttbr1_el1
				701	ret
				702
				703
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	704	func read_ttbr1_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	705	b read_ttbr1_el2
				706
				707
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	708	func read_ttbr1_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	709	b read_ttbr1_el3
				710
				711
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	712	func write_ttbr1_el1
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	713	msr ttbr1_el1, x0
				714	isb
				715	ret
				716
				717
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	718	func write_ttbr1_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	719	b write_ttbr1_el2
				720
				721
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	722	func write_ttbr1_el3
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	723	b write_ttbr1_el3
				724
				725
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	726	func read_hcr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	727	mrs x0, hcr_el2
				728	ret
				729
				730
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	731	func write_hcr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	732	msr hcr_el2, x0
				733	dsb sy
				734	isb
				735	ret
				736
				737
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	738	func read_cpacr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	739	mrs x0, cpacr_el1
				740	ret
				741
				742
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	743	func write_cpacr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	744	msr cpacr_el1, x0
				745	ret
				746
				747
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	748	func read_cntfrq_el0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	749	mrs x0, cntfrq_el0
				750	ret
				751
				752
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	753	func write_cntfrq_el0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	754	msr cntfrq_el0, x0
				755	ret
				756
				757
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	758	func read_cpuectlr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	759	mrs x0, CPUECTLR_EL1
				760	ret
				761
				762
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	763	func write_cpuectlr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	764	msr CPUECTLR_EL1, x0
				765	dsb sy
				766	isb
				767	ret
				768
				769
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	770	func read_cnthctl_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	771	mrs x0, cnthctl_el2
				772	ret
				773
				774
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	775	func write_cnthctl_el2
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	776	msr cnthctl_el2, x0
				777	ret
				778
				779
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	780	func read_cntfrq
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	781	mrs x0, cntfrq_el0
				782	ret
				783
				784
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	785	func write_cntfrq
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	786	msr cntfrq_el0, x0
				787	ret
				788
				789
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	790	func write_scr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	791	msr scr_el3, x0
				792	dsb sy
				793	isb
				794	ret
				795
				796
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	797	func read_scr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	798	mrs x0, scr_el3
				799	ret
				800
				801
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	802	func read_midr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	803	mrs x0, midr_el1
				804	ret
				805
				806
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	807	func read_mpidr
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	808	mrs x0, mpidr_el1
				809	ret
				810
				811
				812	#if SUPPORT_VFP
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	813	func enable_vfp
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	814	mrs x0, cpacr_el1
				815	orr x0, x0, #CPACR_VFP_BITS
				816	msr cpacr_el1, x0
				817	mrs x0, cptr_el3
				818	mov x1, #AARCH64_CPTR_TFP
				819	bic x0, x0, x1
				820	msr cptr_el3, x0
				821	ret
				822
				823
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	824	func read_fpexc
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	825	b read_fpexc
				826	ret
				827
				828
Andrew Thoelke	38bde41	2014-03-18 13:46:55 +0000	[diff] [blame]	829	func write_fpexc
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	830	b write_fpexc
				831	ret
				832
				833	#endif