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Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Douglas Raillard21362a92016-12-02 13:51:54 +00002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +01009
10OUTPUT_FORMAT(elf32-littlearm)
11OUTPUT_ARCH(arm)
12ENTRY(sp_min_vector_table)
13
14MEMORY {
15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
16}
17
18
19SECTIONS
20{
21 . = BL32_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Soby Mathewec8ac1c2016-05-05 14:32:05 +010023 "BL32_BASE address is not aligned on a page boundary.")
24
25#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
28 *entrypoint.o(.text*)
29 *(.text*)
Yatharth Kochar06460cd2016-06-30 15:02:31 +010030 *(.vectors)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000031 . = NEXT(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010032 __TEXT_END__ = .;
33 } >RAM
34
35 .rodata . : {
36 __RODATA_START__ = .;
37 *(.rodata*)
38
39 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
40 . = ALIGN(4);
41 __RT_SVC_DESCS_START__ = .;
42 KEEP(*(rt_svc_descs))
43 __RT_SVC_DESCS_END__ = .;
44
45 /*
46 * Ensure 4-byte alignment for cpu_ops so that its fields are also
47 * aligned. Also ensure cpu_ops inclusion.
48 */
49 . = ALIGN(4);
50 __CPU_OPS_START__ = .;
51 KEEP(*(cpu_ops))
52 __CPU_OPS_END__ = .;
53
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010054 /* Place pubsub sections for events */
55 . = ALIGN(8);
56#include <pubsub_events.h>
57
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000058 . = NEXT(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010059 __RODATA_END__ = .;
60 } >RAM
61#else
62 ro . : {
63 __RO_START__ = .;
64 *entrypoint.o(.text*)
65 *(.text*)
66 *(.rodata*)
67
68 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
69 . = ALIGN(4);
70 __RT_SVC_DESCS_START__ = .;
71 KEEP(*(rt_svc_descs))
72 __RT_SVC_DESCS_END__ = .;
73
74 /*
75 * Ensure 4-byte alignment for cpu_ops so that its fields are also
76 * aligned. Also ensure cpu_ops inclusion.
77 */
78 . = ALIGN(4);
79 __CPU_OPS_START__ = .;
80 KEEP(*(cpu_ops))
81 __CPU_OPS_END__ = .;
82
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010083 /* Place pubsub sections for events */
84 . = ALIGN(8);
85#include <pubsub_events.h>
86
Yatharth Kochar06460cd2016-06-30 15:02:31 +010087 *(.vectors)
Soby Mathewec8ac1c2016-05-05 14:32:05 +010088 __RO_END_UNALIGNED__ = .;
89
90 /*
91 * Memory page(s) mapped to this section will be marked as
92 * read-only, executable. No RW data from the next section must
93 * creep in. Ensure the rest of the current memory block is unused.
94 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000095 . = NEXT(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010096 __RO_END__ = .;
97 } >RAM
98#endif
99
100 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
101 "cpu_ops not defined for this platform.")
102 /*
103 * Define a linker symbol to mark start of the RW memory area for this
104 * image.
105 */
106 __RW_START__ = . ;
107
108 .data . : {
109 __DATA_START__ = .;
110 *(.data*)
111 __DATA_END__ = .;
112 } >RAM
113
Soby Mathewbf169232017-11-14 14:10:10 +0000114#ifdef BL32_PROGBITS_LIMIT
115 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
116#endif
117
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100118 stacks (NOLOAD) : {
119 __STACKS_START__ = .;
120 *(tzfw_normal_stacks)
121 __STACKS_END__ = .;
122 } >RAM
123
124 /*
125 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000126 * Its base address should be 8-byte aligned for better performance of the
127 * zero-initialization code.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100128 */
Douglas Raillard21362a92016-12-02 13:51:54 +0000129 .bss (NOLOAD) : ALIGN(8) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100130 __BSS_START__ = .;
131 *(.bss*)
132 *(COMMON)
133#if !USE_COHERENT_MEM
134 /*
135 * Bakery locks are stored in normal .bss memory
136 *
137 * Each lock's data is spread across multiple cache lines, one per CPU,
138 * but multiple locks can share the same cache line.
139 * The compiler will allocate enough memory for one CPU's bakery locks,
140 * the remaining cache lines are allocated by the linker script
141 */
142 . = ALIGN(CACHE_WRITEBACK_GRANULE);
143 __BAKERY_LOCK_START__ = .;
144 *(bakery_lock)
145 . = ALIGN(CACHE_WRITEBACK_GRANULE);
146 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
147 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
148 __BAKERY_LOCK_END__ = .;
149#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
150 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
151 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
152#endif
153#endif
154
155#if ENABLE_PMF
156 /*
157 * Time-stamps are stored in normal .bss memory
158 *
159 * The compiler will allocate enough memory for one CPU's time-stamps,
160 * the remaining memory for other CPU's is allocated by the
161 * linker script
162 */
163 . = ALIGN(CACHE_WRITEBACK_GRANULE);
164 __PMF_TIMESTAMP_START__ = .;
165 KEEP(*(pmf_timestamp_array))
166 . = ALIGN(CACHE_WRITEBACK_GRANULE);
167 __PMF_PERCPU_TIMESTAMP_END__ = .;
168 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
169 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
170 __PMF_TIMESTAMP_END__ = .;
171#endif /* ENABLE_PMF */
172
173 __BSS_END__ = .;
174 } >RAM
175
176 /*
177 * The xlat_table section is for full, aligned page tables (4K).
178 * Removing them from .bss avoids forcing 4K alignment on
179 * the .bss section and eliminates the unecessary zero init
180 */
181 xlat_table (NOLOAD) : {
182 *(xlat_table)
183 } >RAM
184
185 __BSS_SIZE__ = SIZEOF(.bss);
186
187#if USE_COHERENT_MEM
188 /*
189 * The base address of the coherent memory section must be page-aligned (4K)
190 * to guarantee that the coherent data are stored on their own pages and
191 * are not mixed with normal data. This is required to set up the correct
192 * memory attributes for the coherent data page tables.
193 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000194 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100195 __COHERENT_RAM_START__ = .;
196 /*
197 * Bakery locks are stored in coherent memory
198 *
199 * Each lock's data is contiguous and fully allocated by the compiler
200 */
201 *(bakery_lock)
202 *(tzfw_coherent_mem)
203 __COHERENT_RAM_END_UNALIGNED__ = .;
204 /*
205 * Memory page(s) mapped to this section will be marked
206 * as device memory. No other unexpected data must creep in.
207 * Ensure the rest of the current memory page is unused.
208 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000209 . = NEXT(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100210 __COHERENT_RAM_END__ = .;
211 } >RAM
212
213 __COHERENT_RAM_UNALIGNED_SIZE__ =
214 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
215#endif
216
217 /*
218 * Define a linker symbol to mark end of the RW memory area for this
219 * image.
220 */
221 __RW_END__ = .;
222
223 __BL32_END__ = .;
224}