Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A73_H |
| 8 | #define CORTEX_A73_H |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 9 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 12 | /* Cortex-A73 midr for revision 0 */ |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A73_MIDR U(0x410FD090) |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ |
| 19 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 20 | #define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6) |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 21 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 22 | /******************************************************************************* |
| 23 | * L2 Memory Error Syndrome register specific definitions. |
| 24 | ******************************************************************************/ |
| 25 | #define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ |
| 26 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 27 | /******************************************************************************* |
| 28 | * CPU implementation defined register specific definitions. |
| 29 | ******************************************************************************/ |
| 30 | #define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 |
| 31 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 32 | #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 33 | |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 34 | #define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1 |
| 35 | |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 36 | #define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 |
| 37 | |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 38 | /******************************************************************************* |
| 39 | * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs |
| 40 | ******************************************************************************/ |
Balint Dobszay | b669361 | 2019-10-11 14:01:43 +0200 | [diff] [blame] | 41 | #ifndef __ASSEMBLER__ |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 42 | DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) |
Balint Dobszay | b669361 | 2019-10-11 14:01:43 +0200 | [diff] [blame] | 43 | #endif /* __ASSEMBLER__ */ |
developer | a21d47e | 2019-05-02 19:29:25 +0800 | [diff] [blame] | 44 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 45 | #endif /* CORTEX_A73_H */ |