Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | #include <inttypes.h> |
| 10 | |
| 11 | #include <drivers/scmi-msg.h> |
| 12 | #include <drivers/scmi.h> |
Amit Nagal | acb6b92 | 2024-07-28 20:32:58 -1200 | [diff] [blame] | 13 | #include <lib/mmio.h> |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 14 | #include <lib/utils_def.h> |
| 15 | #include <platform_def.h> |
| 16 | #include <scmi.h> |
| 17 | |
| 18 | #include "plat_private.h" |
| 19 | |
| 20 | #define HIGH (1) |
| 21 | #define LOW (0) |
| 22 | |
| 23 | struct scmi_clk { |
| 24 | unsigned long clock_id; |
| 25 | unsigned long rate; |
| 26 | const char *name; |
| 27 | bool enabled; |
| 28 | }; |
| 29 | |
| 30 | #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \ |
| 31 | [_scmi_id] = { \ |
| 32 | .clock_id = (_id), \ |
| 33 | .name = (_name), \ |
| 34 | .enabled = (_init_enabled), \ |
| 35 | .rate = (_rate), \ |
| 36 | } |
| 37 | |
| 38 | static struct scmi_clk scmi0_clock[] = { |
| 39 | CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000), |
| 40 | CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000), |
| 41 | CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000), |
| 42 | CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000), |
| 43 | CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000), |
| 44 | CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000), |
| 45 | CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000), |
| 46 | CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000), |
| 47 | CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000), |
| 48 | CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000), |
| 49 | CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000), |
| 50 | CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000), |
| 51 | CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), |
| 52 | CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), |
| 53 | CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), |
| 54 | CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000), |
| 55 | CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000), |
| 56 | CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), |
| 57 | CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), |
| 58 | CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), |
| 59 | CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000), |
| 60 | CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000), |
| 61 | CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000), |
| 62 | CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000), |
| 63 | CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000), |
| 64 | CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000), |
| 65 | CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000), |
| 66 | CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000), |
| 67 | CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000), |
| 68 | CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000), |
| 69 | CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000), |
| 70 | CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000), |
| 71 | CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000), |
| 72 | CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000), |
| 73 | CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000), |
| 74 | CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000), |
| 75 | CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000), |
| 76 | CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000), |
| 77 | CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000), |
| 78 | CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000), |
| 79 | CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000), |
| 80 | CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000), |
| 81 | CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000), |
| 82 | CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000), |
| 83 | CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000), |
| 84 | CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000), |
| 85 | CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000), |
| 86 | CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000), |
| 87 | CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000), |
| 88 | CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000), |
| 89 | CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000), |
| 90 | CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000), |
| 91 | CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000), |
| 92 | CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000), |
| 93 | CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000), |
| 94 | CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000), |
| 95 | CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000), |
| 96 | CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000), |
| 97 | CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000), |
| 98 | CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000), |
| 99 | CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000), |
| 100 | CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000), |
| 101 | CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000), |
| 102 | CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000), |
| 103 | CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000), |
| 104 | CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000), |
| 105 | CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000), |
| 106 | CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000), |
| 107 | CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000), |
| 108 | CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000), |
| 109 | CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000), |
| 110 | CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000), |
| 111 | CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000), |
| 112 | CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000), |
| 113 | CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000), |
| 114 | CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000), |
| 115 | CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000), |
| 116 | CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000), |
| 117 | CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000), |
| 118 | CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000), |
| 119 | CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000), |
| 120 | CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000), |
| 121 | CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000), |
| 122 | CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000), |
| 123 | CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000), |
| 124 | CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000), |
| 125 | CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000), |
| 126 | CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000), |
| 127 | CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000), |
| 128 | CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000), |
| 129 | }; |
| 130 | |
| 131 | /* |
| 132 | * struct scmi_reset - Data for the exposed reset controller |
| 133 | * @reset_id: Reset identifier in RCC reset driver |
| 134 | * @name: Reset string ID exposed to agent |
| 135 | */ |
| 136 | struct scmi_reset { |
| 137 | unsigned long reset_id; |
| 138 | const char *name; |
| 139 | }; |
| 140 | |
| 141 | #define RESET_CELL(_scmi_id, _id, _name) \ |
| 142 | [_scmi_id] = { \ |
| 143 | .reset_id = (_id), \ |
| 144 | .name = (_name), \ |
| 145 | } |
| 146 | |
| 147 | static struct scmi_reset scmi0_reset[] = { |
| 148 | RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"), |
| 149 | RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"), |
| 150 | RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"), |
| 151 | RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"), |
| 152 | RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"), |
| 153 | RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"), |
| 154 | RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"), |
| 155 | RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"), |
| 156 | RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"), |
| 157 | RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"), |
| 158 | RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"), |
| 159 | RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"), |
| 160 | RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"), |
| 161 | RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"), |
| 162 | RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"), |
| 163 | RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"), |
| 164 | RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"), |
| 165 | RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"), |
| 166 | RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"), |
| 167 | RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"), |
| 168 | RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"), |
| 169 | RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"), |
| 170 | RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"), |
| 171 | RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"), |
| 172 | RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"), |
| 173 | RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"), |
| 174 | RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"), |
| 175 | RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"), |
| 176 | RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"), |
| 177 | RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"), |
| 178 | RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"), |
| 179 | RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"), |
| 180 | RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"), |
| 181 | RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"), |
| 182 | RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"), |
Amit Nagal | acb6b92 | 2024-07-28 20:32:58 -1200 | [diff] [blame] | 183 | RESET_CELL(RESET_UFSPHY_0, RESET_UFSPHY_0, "ufsphy0"), |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 184 | }; |
| 185 | |
Michal Simek | 9aaf773 | 2024-02-02 11:26:14 +0100 | [diff] [blame] | 186 | /** |
| 187 | * struct scmi_pd - Data for the exposed power domain controller |
| 188 | * @pd_id: pd identifier in RCC reset driver |
| 189 | * @name: pd string ID exposed to agent |
| 190 | * @state: keep state setting |
| 191 | */ |
| 192 | struct scmi_pd { |
| 193 | unsigned long pd_id; |
| 194 | const char *name; |
| 195 | unsigned int state; |
| 196 | }; |
| 197 | |
| 198 | #define PD_CELL(_scmi_id, _id, _name, _state) \ |
| 199 | [_scmi_id] = { \ |
| 200 | .pd_id = _id, \ |
| 201 | .name = _name, \ |
| 202 | .state = _state, \ |
| 203 | } |
| 204 | |
| 205 | static struct scmi_pd scmi0_pd[] = { |
| 206 | PD_CELL(PD_USB0, PD_USB0, "usb0", 0), |
| 207 | PD_CELL(PD_USB1, PD_USB1, "usb1", 0), |
| 208 | }; |
| 209 | |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 210 | struct scmi_resources { |
| 211 | struct scmi_clk *clock; |
| 212 | size_t clock_count; |
| 213 | struct scmi_reset *reset; |
| 214 | size_t reset_count; |
Michal Simek | 9aaf773 | 2024-02-02 11:26:14 +0100 | [diff] [blame] | 215 | struct scmi_pd *pd; |
| 216 | size_t pd_count; |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | static const struct scmi_resources resources[] = { |
| 220 | [0] = { |
| 221 | .clock = scmi0_clock, |
| 222 | .clock_count = ARRAY_SIZE(scmi0_clock), |
| 223 | .reset = scmi0_reset, |
| 224 | .reset_count = ARRAY_SIZE(scmi0_reset), |
Michal Simek | 9aaf773 | 2024-02-02 11:26:14 +0100 | [diff] [blame] | 225 | .pd = scmi0_pd, |
| 226 | .pd_count = ARRAY_SIZE(scmi0_pd), |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 227 | }, |
| 228 | }; |
| 229 | |
| 230 | static const struct scmi_resources *find_resource(unsigned int agent_id) |
| 231 | { |
| 232 | assert(agent_id < ARRAY_SIZE(resources)); |
| 233 | |
| 234 | return &resources[agent_id]; |
| 235 | } |
| 236 | |
| 237 | static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id) |
| 238 | { |
| 239 | const struct scmi_resources *resource = find_resource(agent_id); |
| 240 | size_t n = 0U; |
| 241 | struct scmi_clk *ret = NULL; |
| 242 | |
| 243 | if (resource != NULL) { |
| 244 | for (n = 0U; n < resource->clock_count; n++) { |
| 245 | if (n == scmi_id) { |
| 246 | ret = &resource->clock[n]; |
| 247 | break; |
| 248 | } |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | return ret; |
| 253 | } |
| 254 | |
| 255 | size_t plat_scmi_clock_count(unsigned int agent_id) |
| 256 | { |
| 257 | const struct scmi_resources *resource = find_resource(agent_id); |
| 258 | size_t ret; |
| 259 | |
| 260 | if (resource == NULL) { |
| 261 | ret = 0U; |
| 262 | } else { |
| 263 | VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count); |
| 264 | |
| 265 | ret = resource->clock_count; |
| 266 | } |
| 267 | return ret; |
| 268 | } |
| 269 | |
| 270 | const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id) |
| 271 | { |
| 272 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 273 | const char *ret; |
| 274 | |
| 275 | if (clock == NULL) { |
| 276 | ret = NULL; |
| 277 | } else { |
| 278 | VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name); |
| 279 | |
| 280 | ret = clock->name; |
| 281 | } |
| 282 | return ret; |
| 283 | }; |
| 284 | |
| 285 | /* Called by Linux */ |
| 286 | int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, |
| 287 | unsigned long *array, size_t *nb_elts, |
| 288 | uint32_t start_idx) |
| 289 | { |
| 290 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 291 | |
| 292 | if (clock == NULL) { |
| 293 | return SCMI_NOT_FOUND; |
| 294 | } |
| 295 | |
| 296 | if (start_idx > 0) { |
| 297 | return SCMI_OUT_OF_RANGE; |
| 298 | } |
| 299 | |
| 300 | if (array == NULL) { |
| 301 | *nb_elts = 1U; |
| 302 | } else if (*nb_elts == 1U) { |
| 303 | *array = clock->rate; |
| 304 | VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n", |
| 305 | scmi_id, clock->name, *array); |
| 306 | } else { |
| 307 | return SCMI_GENERIC_ERROR; |
| 308 | } |
| 309 | |
| 310 | return SCMI_SUCCESS; |
| 311 | } |
| 312 | |
| 313 | unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id) |
| 314 | { |
| 315 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 316 | unsigned long ret; |
| 317 | |
| 318 | if ((clock == NULL)) { |
| 319 | ret = SCMI_NOT_FOUND; |
| 320 | } else { |
| 321 | VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate); |
| 322 | ret = clock->rate; |
| 323 | } |
| 324 | return ret; |
| 325 | } |
| 326 | |
| 327 | int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id, |
| 328 | unsigned long rate) |
| 329 | { |
| 330 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 331 | unsigned long ret = UL(SCMI_SUCCESS); |
| 332 | |
| 333 | if ((clock == NULL)) { |
| 334 | ret = SCMI_NOT_FOUND; |
| 335 | } else { |
| 336 | VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate); |
| 337 | clock->rate = rate; |
| 338 | } |
| 339 | return ret; |
| 340 | } |
| 341 | |
| 342 | int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) |
| 343 | { |
| 344 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 345 | int32_t ret; |
| 346 | |
| 347 | if ((clock == NULL)) { |
| 348 | ret = SCMI_NOT_FOUND; |
| 349 | } else { |
| 350 | VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled); |
| 351 | |
| 352 | if (clock->enabled) { |
| 353 | ret = HIGH; |
| 354 | } else { |
| 355 | ret = LOW; |
| 356 | } |
| 357 | } |
| 358 | return ret; |
| 359 | } |
| 360 | |
| 361 | int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, |
| 362 | bool enable_not_disable) |
| 363 | { |
| 364 | struct scmi_clk *clock = clk_find(agent_id, scmi_id); |
| 365 | int32_t ret; |
| 366 | |
| 367 | if (clock == NULL) { |
| 368 | ret = SCMI_NOT_FOUND; |
| 369 | } else { |
| 370 | if (enable_not_disable) { |
| 371 | if (!clock->enabled) { |
| 372 | VERBOSE("SCMI: clock: %u enable\n", scmi_id); |
| 373 | clock->enabled = true; |
| 374 | } |
| 375 | } else { |
| 376 | if (clock->enabled) { |
| 377 | VERBOSE("SCMI: clock: %u disable\n", scmi_id); |
| 378 | clock->enabled = false; |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled); |
| 383 | |
| 384 | ret = SCMI_SUCCESS; |
| 385 | } |
| 386 | |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | |
| 391 | /* |
| 392 | * Platform SCMI reset domains |
| 393 | */ |
| 394 | static struct scmi_reset *find_reset(unsigned int agent_id, |
| 395 | unsigned int scmi_id) |
| 396 | { |
| 397 | const struct scmi_resources *resource = find_resource(agent_id); |
| 398 | size_t n; |
| 399 | |
| 400 | if (resource != NULL) { |
| 401 | for (n = 0U; n < resource->reset_count; n++) { |
| 402 | if (n == scmi_id) { |
| 403 | return &resource->reset[n]; |
| 404 | } |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | return NULL; |
| 409 | } |
| 410 | |
| 411 | const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id) |
| 412 | { |
| 413 | const struct scmi_reset *reset = find_reset(agent_id, scmi_id); |
| 414 | |
| 415 | if (reset == NULL) { |
| 416 | return NULL; |
| 417 | } |
| 418 | |
| 419 | return reset->name; |
| 420 | } |
| 421 | |
| 422 | size_t plat_scmi_rstd_count(unsigned int agent_id) |
| 423 | { |
| 424 | const struct scmi_resources *resource = find_resource(agent_id); |
| 425 | |
| 426 | if (resource == NULL) { |
| 427 | return 0U; |
| 428 | } |
| 429 | |
| 430 | return resource->reset_count; |
| 431 | } |
| 432 | |
| 433 | int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, |
| 434 | uint32_t state) |
| 435 | { |
| 436 | const struct scmi_reset *reset = find_reset(agent_id, scmi_id); |
| 437 | |
| 438 | if (reset == NULL) { |
| 439 | return SCMI_NOT_FOUND; |
| 440 | } |
| 441 | |
| 442 | /* Supports only reset with context loss */ |
| 443 | if (state != 0U) { |
| 444 | return SCMI_NOT_SUPPORTED; |
| 445 | } |
| 446 | |
| 447 | NOTICE("SCMI reset on ID %lu/%s\n", |
| 448 | reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); |
| 449 | |
| 450 | return SCMI_SUCCESS; |
| 451 | } |
| 452 | |
| 453 | int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, |
| 454 | bool assert_not_deassert) |
| 455 | { |
| 456 | const struct scmi_reset *reset = find_reset(agent_id, scmi_id); |
| 457 | |
| 458 | if (reset == NULL) { |
| 459 | return SCMI_NOT_FOUND; |
| 460 | } |
| 461 | |
| 462 | if (assert_not_deassert) { |
| 463 | NOTICE("SCMI reset %lu/%s set\n", |
| 464 | reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); |
Amit Nagal | acb6b92 | 2024-07-28 20:32:58 -1200 | [diff] [blame] | 465 | |
| 466 | switch (scmi_id) { |
| 467 | case RESET_UFS0_0: |
| 468 | mmio_write_32(PMXC_CRP_RST_UFS, 1); |
| 469 | break; |
| 470 | case RESET_UFSPHY_0: |
| 471 | mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 1); |
| 472 | break; |
| 473 | default: |
| 474 | break; |
| 475 | } |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 476 | } else { |
| 477 | NOTICE("SCMI reset %lu/%s release\n", |
| 478 | reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); |
Amit Nagal | acb6b92 | 2024-07-28 20:32:58 -1200 | [diff] [blame] | 479 | |
| 480 | switch (scmi_id) { |
| 481 | case RESET_UFS0_0: |
| 482 | mmio_write_32(PMXC_CRP_RST_UFS, 0); |
| 483 | break; |
| 484 | case RESET_UFSPHY_0: |
| 485 | mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 0); |
| 486 | break; |
| 487 | default: |
| 488 | break; |
| 489 | } |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 490 | } |
| 491 | |
| 492 | return SCMI_SUCCESS; |
| 493 | } |
| 494 | |
Michal Simek | 9aaf773 | 2024-02-02 11:26:14 +0100 | [diff] [blame] | 495 | /* |
| 496 | * Platform SCMI reset domains |
| 497 | */ |
| 498 | static struct scmi_pd *find_pd(unsigned int agent_id, unsigned int pd_id) |
| 499 | { |
| 500 | const struct scmi_resources *resource = find_resource(agent_id); |
| 501 | size_t n; |
| 502 | |
| 503 | if (resource != NULL) { |
| 504 | for (n = 0U; n < resource->pd_count; n++) { |
| 505 | if (n == pd_id) { |
| 506 | return &resource->pd[n]; |
| 507 | } |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | return NULL; |
| 512 | } |
| 513 | |
| 514 | size_t plat_scmi_pd_count(unsigned int agent_id) |
| 515 | { |
| 516 | const struct scmi_resources *resource = find_resource(agent_id); |
| 517 | size_t ret; |
| 518 | |
| 519 | if (resource == NULL) { |
| 520 | ret = 0U; |
| 521 | } else { |
| 522 | ret = resource->pd_count; |
| 523 | |
| 524 | NOTICE("SCMI: PD: %d\n", (unsigned int)ret); |
| 525 | } |
| 526 | return ret; |
| 527 | } |
| 528 | |
| 529 | const char *plat_scmi_pd_get_name(unsigned int agent_id, unsigned int pd_id) |
| 530 | { |
| 531 | const struct scmi_pd *pd = find_pd(agent_id, pd_id); |
| 532 | |
| 533 | if (pd == NULL) { |
| 534 | return NULL; |
| 535 | } |
| 536 | |
| 537 | return pd->name; |
| 538 | } |
| 539 | |
| 540 | unsigned int plat_scmi_pd_statistics(unsigned int agent_id, unsigned long *pd_id) |
| 541 | { |
| 542 | return 0U; |
| 543 | } |
| 544 | |
| 545 | unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id, unsigned int pd_id) |
| 546 | { |
| 547 | return 0U; |
| 548 | } |
| 549 | |
| 550 | unsigned int plat_scmi_pd_get_state(unsigned int agent_id, unsigned int pd_id) |
| 551 | { |
| 552 | const struct scmi_pd *pd = find_pd(agent_id, pd_id); |
| 553 | |
| 554 | if (pd == NULL) { |
| 555 | return SCMI_NOT_SUPPORTED; |
| 556 | } |
| 557 | |
| 558 | NOTICE("SCMI: PD: get id: %d, state: %x\n", pd_id, pd->state); |
| 559 | |
| 560 | return pd->state; |
| 561 | } |
| 562 | |
| 563 | int32_t plat_scmi_pd_set_state(unsigned int agent_id, unsigned int flags, unsigned int pd_id, |
| 564 | unsigned int state) |
| 565 | { |
| 566 | struct scmi_pd *pd = find_pd(agent_id, pd_id); |
| 567 | |
| 568 | if (pd == NULL) { |
| 569 | return SCMI_NOT_SUPPORTED; |
| 570 | } |
| 571 | |
| 572 | NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n", |
| 573 | pd_id, pd->state, state, flags); |
| 574 | |
| 575 | pd->state = state; |
| 576 | |
| 577 | return 0U; |
| 578 | } |
| 579 | |
| 580 | |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 581 | /* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */ |
| 582 | static struct scmi_msg_channel scmi_channel[] = { |
| 583 | [0] = { |
| 584 | .shm_addr = SMT_BUFFER_BASE, |
| 585 | .shm_size = SMT_BUF_SLOT_SIZE, |
| 586 | }, |
| 587 | }; |
| 588 | |
| 589 | struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) |
| 590 | { |
| 591 | assert(agent_id < ARRAY_SIZE(scmi_channel)); |
| 592 | |
| 593 | VERBOSE("%d: SCMI asking for channel\n", agent_id); |
| 594 | |
| 595 | /* Just in case that code is reused */ |
| 596 | return &scmi_channel[agent_id]; |
| 597 | } |
| 598 | |
| 599 | /* Base protocol implementations */ |
| 600 | const char *plat_scmi_vendor_name(void) |
| 601 | { |
| 602 | return SCMI_VENDOR; |
| 603 | } |
| 604 | |
| 605 | const char *plat_scmi_sub_vendor_name(void) |
| 606 | { |
| 607 | return SCMI_PRODUCT; |
| 608 | } |
| 609 | |
| 610 | /* Currently supporting Clocks and Reset Domains */ |
| 611 | static const uint8_t plat_protocol_list[] = { |
| 612 | SCMI_PROTOCOL_ID_BASE, |
| 613 | SCMI_PROTOCOL_ID_CLOCK, |
| 614 | SCMI_PROTOCOL_ID_RESET_DOMAIN, |
Michal Simek | 9aaf773 | 2024-02-02 11:26:14 +0100 | [diff] [blame] | 615 | SCMI_PROTOCOL_ID_POWER_DOMAIN, |
| 616 | /* SCMI_PROTOCOL_ID_SENSOR, */ |
Amit Nagal | 055796f | 2024-06-05 12:32:38 +0530 | [diff] [blame] | 617 | 0U /* Null termination */ |
| 618 | }; |
| 619 | |
| 620 | size_t plat_scmi_protocol_count(void) |
| 621 | { |
| 622 | const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; |
| 623 | |
| 624 | VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count); |
| 625 | |
| 626 | return count; |
| 627 | } |
| 628 | |
| 629 | const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) |
| 630 | { |
| 631 | return plat_protocol_list; |
| 632 | } |
| 633 | |
| 634 | void init_scmi_server(void) |
| 635 | { |
| 636 | size_t i; |
| 637 | int32_t ret; |
| 638 | |
| 639 | for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) |
| 640 | scmi_smt_init_agent_channel(&scmi_channel[i]); |
| 641 | |
| 642 | INFO("SCMI: Server initialized\n"); |
| 643 | |
| 644 | if (platform_id == QEMU) { |
| 645 | /* default setting is for QEMU */ |
| 646 | } else if (platform_id == SPP) { |
| 647 | for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) { |
| 648 | |
| 649 | /* Keep i2c on 100MHz to calculate rates properly */ |
| 650 | if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0) |
| 651 | continue; |
| 652 | /* |
| 653 | * SPP supports multiple versions. |
| 654 | * The cpu_clock value is set to corresponding SPP |
| 655 | * version in early platform setup, resuse the same |
| 656 | * value here. |
| 657 | */ |
| 658 | ret = plat_scmi_clock_set_rate(0, i, cpu_clock); |
| 659 | if (ret < 0) { |
| 660 | NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i); |
| 661 | } |
| 662 | } |
| 663 | } else { |
| 664 | /* Making MISRA C 2012 15.7 compliant */ |
| 665 | } |
| 666 | } |