blob: 9329fff25b8e023ecfd000a85ba88b0006a70793 [file] [log] [blame]
Yann Gautier40ff1382024-05-21 20:54:04 +02001/*
2 * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP2_DDR_HELPERS_H
8#define STM32MP2_DDR_HELPERS_H
9
Nicolas Le Bayon068d3412021-07-01 14:44:22 +020010#include <stdbool.h>
11#include <stdint.h>
12
13#include <drivers/st/stm32mp2_ddr_regs.h>
14
15enum stm32mp2_ddr_sr_mode {
16 DDR_SR_MODE_INVALID = 0,
17 DDR_SSR_MODE,
18 DDR_HSR_MODE,
19 DDR_ASR_MODE,
20};
21
22void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
23void ddr_wait_lp3_mode(bool state);
24int ddr_sr_exit_loop(void);
25uint32_t ddr_get_io_calibration_val(void);
26int ddr_sr_entry(bool standby);
27int ddr_sr_exit(void);
28enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);
29void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode);
30void ddr_save_sr_mode(void);
31void ddr_restore_sr_mode(void);
Yann Gautier40ff1382024-05-21 20:54:04 +020032void ddr_sub_system_clk_init(void);
Nicolas Le Bayon068d3412021-07-01 14:44:22 +020033void ddr_sub_system_clk_off(void);
Yann Gautier40ff1382024-05-21 20:54:04 +020034
35#endif /* STM32MP2_DDR_HELPERS_H */