Yann Gautier | 40ff138 | 2024-05-21 20:54:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2024, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP2_DDR_HELPERS_H |
| 8 | #define STM32MP2_DDR_HELPERS_H |
| 9 | |
Nicolas Le Bayon | 068d341 | 2021-07-01 14:44:22 +0200 | [diff] [blame] | 10 | #include <stdbool.h> |
| 11 | #include <stdint.h> |
| 12 | |
| 13 | #include <drivers/st/stm32mp2_ddr_regs.h> |
| 14 | |
| 15 | enum stm32mp2_ddr_sr_mode { |
| 16 | DDR_SR_MODE_INVALID = 0, |
| 17 | DDR_SSR_MODE, |
| 18 | DDR_HSR_MODE, |
| 19 | DDR_ASR_MODE, |
| 20 | }; |
| 21 | |
| 22 | void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry); |
| 23 | void ddr_wait_lp3_mode(bool state); |
| 24 | int ddr_sr_exit_loop(void); |
| 25 | uint32_t ddr_get_io_calibration_val(void); |
| 26 | int ddr_sr_entry(bool standby); |
| 27 | int ddr_sr_exit(void); |
| 28 | enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void); |
| 29 | void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode); |
| 30 | void ddr_save_sr_mode(void); |
| 31 | void ddr_restore_sr_mode(void); |
Yann Gautier | 40ff138 | 2024-05-21 20:54:04 +0200 | [diff] [blame] | 32 | void ddr_sub_system_clk_init(void); |
Nicolas Le Bayon | 068d341 | 2021-07-01 14:44:22 +0200 | [diff] [blame] | 33 | void ddr_sub_system_clk_off(void); |
Yann Gautier | 40ff138 | 2024-05-21 20:54:04 +0200 | [diff] [blame] | 34 | |
| 35 | #endif /* STM32MP2_DDR_HELPERS_H */ |