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Varun Wadekar28463b92015-07-14 17:11:20 +05301/*
Varun Wadekar2b914122018-06-25 11:36:47 -07002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar28463b92015-07-14 17:11:20 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar28463b92015-07-14 17:11:20 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef DENVER_H
8#define DENVER_H
Varun Wadekar28463b92015-07-14 17:11:20 +05309
Varun Wadekar3c337a62015-09-03 17:15:06 +053010/* MIDR values for Denver */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070011#define DENVER_MIDR_PN0 U(0x4E0F0000)
12#define DENVER_MIDR_PN1 U(0x4E0F0010)
13#define DENVER_MIDR_PN2 U(0x4E0F0020)
14#define DENVER_MIDR_PN3 U(0x4E0F0030)
15#define DENVER_MIDR_PN4 U(0x4E0F0040)
Alex Van Brunt5f68fa72019-07-23 10:00:42 -070016#define DENVER_MIDR_PN5 U(0x4E0F0050)
17#define DENVER_MIDR_PN6 U(0x4E0F0060)
18#define DENVER_MIDR_PN7 U(0x4E0F0070)
19#define DENVER_MIDR_PN8 U(0x4E0F0080)
Hemant Nigam96e081d2019-12-17 14:21:38 -080020#define DENVER_MIDR_PN9 U(0x4E0F0090)
Varun Wadekar3c337a62015-09-03 17:15:06 +053021
22/* Implementer code in the MIDR register */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070023#define DENVER_IMPL U(0x4E)
Varun Wadekar28463b92015-07-14 17:11:20 +053024
25/* CPU state ids - implementation defined */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070026#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
Varun Wadekar28463b92015-07-14 17:11:20 +053027
Varun Wadekarcd38e6e2018-08-28 09:11:30 -070028/* Speculative store buffering */
29#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
30#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
31
32/* Speculative memory disambiguation */
33#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
34#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
35
Varun Wadekar2b914122018-06-25 11:36:47 -070036/* Core power management states */
37#define DENVER_CPU_PMSTATE_C1 U(0x1)
38#define DENVER_CPU_PMSTATE_C6 U(0x6)
39#define DENVER_CPU_PMSTATE_C7 U(0x7)
40#define DENVER_CPU_PMSTATE_MASK U(0xF)
41
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -070042/* ACTRL_ELx bits to enable dual execution*/
43#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
44#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
45#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
46
Julius Werner53456fc2019-07-09 13:49:11 -070047#ifndef __ASSEMBLER__
Varun Wadekard43583c2016-02-22 11:09:41 -080048
49/* Disable Dynamic Code Optimisation */
50void denver_disable_dco(void);
51
Julius Werner53456fc2019-07-09 13:49:11 -070052#endif /* __ASSEMBLER__ */
Varun Wadekard43583c2016-02-22 11:09:41 -080053
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000054#endif /* DENVER_H */