| developer | afa342e | 2020-12-14 17:41:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(C)2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MT_SPM_VCOREFS_H |
| 8 | #define MT_SPM_VCOREFS_H |
| 9 | |
| 10 | uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4); |
| 11 | |
| 12 | enum vcorefs_smc_cmd { |
| 13 | VCOREFS_SMC_CMD_0, |
| 14 | VCOREFS_SMC_CMD_1, |
| 15 | VCOREFS_SMC_CMD_2, |
| 16 | VCOREFS_SMC_CMD_3, |
| 17 | VCOREFS_SMC_CMD_4, |
| 18 | /* check spmfw status */ |
| 19 | VCOREFS_SMC_CMD_5, |
| 20 | |
| 21 | /* get spmfw type */ |
| 22 | VCOREFS_SMC_CMD_6, |
| 23 | |
| 24 | /* get spm reg status */ |
| 25 | VCOREFS_SMC_CMD_7, |
| 26 | |
| 27 | NUM_VCOREFS_SMC_CMD, |
| 28 | }; |
| 29 | |
| 30 | enum vcorefs_smc_cmd_new { |
| 31 | VCOREFS_SMC_CMD_INIT = 0, |
| 32 | VCOREFS_SMC_CMD_KICK = 1, |
| 33 | }; |
| 34 | |
| 35 | #define _VCORE_BASE_UV 400000 |
| 36 | #define _VCORE_STEP_UV 6250 |
| 37 | |
| 38 | /* PMIC */ |
| 39 | #define __vcore_pmic_to_uv(pmic) \ |
| 40 | (((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV) |
| 41 | |
| 42 | #define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \ |
| 43 | ((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV) |
| 44 | |
| 45 | struct reg_config { |
| 46 | uint32_t offset; |
| 47 | uint32_t val; |
| 48 | }; |
| 49 | |
| 50 | #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) |
| 51 | #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) |
| 52 | #define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8) |
| 53 | #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC) |
| 54 | #define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0) |
| 55 | #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4) |
| 56 | #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) |
| 57 | #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100) |
| 58 | #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104) |
| 59 | #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108) |
| 60 | #define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C) |
| 61 | #define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110) |
| 62 | #define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114) |
| 63 | #define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118) |
| 64 | #define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C) |
| 65 | #define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280) |
| 66 | #define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294) |
| 67 | #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) |
| 68 | #define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614) |
| 69 | #define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00) |
| 70 | #define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04) |
| 71 | #define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08) |
| 72 | #define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C) |
| 73 | #define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10) |
| 74 | #define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14) |
| 75 | #define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18) |
| 76 | #define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34) |
| 77 | #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) |
| 78 | #define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C) |
| 79 | #define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40) |
| 80 | #define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44) |
| 81 | #define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60) |
| 82 | #define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4) |
| 83 | #define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8) |
| 84 | #define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC) |
| 85 | #define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0) |
| 86 | #define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4) |
| 87 | #define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8) |
| 88 | #define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC) |
| 89 | #define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0) |
| 90 | #define DVFSRC_LAST (DVFSRC_BASE + 0xAE4) |
| 91 | #define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8) |
| 92 | #define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC) |
| 93 | #define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0) |
| 94 | #define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4) |
| 95 | #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) |
| 96 | #define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC) |
| 97 | #define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00) |
| 98 | #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) |
| 99 | #define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08) |
| 100 | #define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C) |
| 101 | #define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0) |
| 102 | #define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4) |
| 103 | #define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8) |
| 104 | #define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC) |
| 105 | #define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00) |
| 106 | #define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04) |
| 107 | #define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08) |
| 108 | #define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C) |
| 109 | #define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0) |
| 110 | #define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4) |
| 111 | #define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8) |
| 112 | #define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC) |
| 113 | #define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00) |
| 114 | #define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04) |
| 115 | #define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08) |
| 116 | #define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C) |
| 117 | #define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10) |
| 118 | #define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14) |
| 119 | #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) |
| 120 | #define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C) |
| 121 | #define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38) |
| 122 | #define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C) |
| 123 | #define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C) |
| 124 | #define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50) |
| 125 | #define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54) |
| 126 | #define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58) |
| 127 | #define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C) |
| 128 | #define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60) |
| 129 | #define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64) |
| 130 | #define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68) |
| 131 | #define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C) |
| 132 | |
| 133 | #define VCORE_VB_EFUSE (0x11C105E8) |
| 134 | |
| 135 | #endif /* MT_SPM_VCOREFS_H */ |