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Vikram Kanigiri510d87b2016-01-29 12:32:58 +00001/*
Summer Qin5ce394c2018-03-12 11:28:26 +08002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00005 */
6
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <common/debug.h>
12#include <drivers/arm/tzc_dmc500.h>
13
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <plat_arm.h>
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000015
16/*******************************************************************************
17 * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000018 * When booting an EL3 payload, this is simplified: we configure region 0 with
19 * secure access only and do not enable any other region.
20 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080021void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
22 const arm_tzc_regions_info_t *tzc_regions)
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000023{
Summer Qin5ce394c2018-03-12 11:28:26 +080024#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010025 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080026 const arm_tzc_regions_info_t *p;
27 const arm_tzc_regions_info_t init_tzc_regions[] = {
28 ARM_TZC_REGIONS_DEF,
29 {0}
30 };
31#endif
32
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000033 assert(plat_driver_data);
34
35 INFO("Configuring DMC-500 TZ Settings\n");
36
37 tzc_dmc500_driver_init(plat_driver_data);
38
39#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080040 if (tzc_regions == NULL)
41 p = init_tzc_regions;
42 else
43 p = tzc_regions;
44
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000045 /* Region 0 set to no access by default */
46 tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
47
Summer Qin5ce394c2018-03-12 11:28:26 +080048 /* Rest Regions set according to tzc_regions array */
49 for (; p->base != 0ULL; p++) {
50 tzc_dmc500_configure_region(region_index, p->base, p->end,
51 p->sec_attr, p->nsaid_permissions);
52 region_index++;
53 }
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000054
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010055 INFO("Total %u regions set.\n", region_index);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000056
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000057#else
58 /* Allow secure access only to DRAM for EL3 payloads */
59 tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
60#endif
61 /*
62 * Raise an exception if a NS device tries to access secure memory
63 * TODO: Add interrupt handling support.
64 */
65 tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
66
67 /*
68 * Flush the configuration settings to have an affect. Validate
69 * flush by checking FILTER_EN is set on region 1 attributes
70 * register.
71 */
72 tzc_dmc500_config_complete();
73
74 /*
75 * Wait for the flush to complete.
76 * TODO: Have a timeout for this loop
77 */
78 while (tzc_dmc500_verify_complete())
79 ;
80}