kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
Kalyani Chidambaram Vaidyanathan | 1b3fa45 | 2023-01-30 17:44:26 -0800 | [diff] [blame] | 3 | * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 8 | #include <inttypes.h> |
| 9 | #include <stdint.h> |
| 10 | |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 11 | #include <arch.h> |
| 12 | #include <arch_helpers.h> |
| 13 | #include <assert.h> |
| 14 | #include <common/bl_common.h> |
| 15 | #include <common/debug.h> |
| 16 | #include <common/runtime_svc.h> |
| 17 | #include <errno.h> |
Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 18 | #include <lib/mmio.h> |
| 19 | #include <lib/utils_def.h> |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 20 | |
| 21 | #include <memctrl.h> |
| 22 | #include <pmc.h> |
| 23 | #include <tegra_private.h> |
| 24 | #include <tegra_platform.h> |
| 25 | #include <tegra_def.h> |
| 26 | |
| 27 | /******************************************************************************* |
| 28 | * PMC parameters |
| 29 | ******************************************************************************/ |
| 30 | #define PMC_READ U(0xaa) |
| 31 | #define PMC_WRITE U(0xbb) |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * Tegra210 SiP SMCs |
| 35 | ******************************************************************************/ |
Kalyani Chidambaram Vaidyanathan | 1b3fa45 | 2023-01-30 17:44:26 -0800 | [diff] [blame] | 36 | #define TEGRA_SIP_PMC_COMMANDS_LEGACY U(0xC2FEFE00) |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 37 | #define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00) |
| 38 | |
| 39 | /******************************************************************************* |
| 40 | * This function is responsible for handling all T210 SiP calls |
| 41 | ******************************************************************************/ |
| 42 | int plat_sip_handler(uint32_t smc_fid, |
| 43 | uint64_t x1, |
| 44 | uint64_t x2, |
| 45 | uint64_t x3, |
| 46 | uint64_t x4, |
| 47 | const void *cookie, |
| 48 | void *handle, |
| 49 | uint64_t flags) |
| 50 | { |
| 51 | uint32_t val, ns; |
| 52 | |
| 53 | /* Determine which security state this SMC originated from */ |
| 54 | ns = is_caller_non_secure(flags); |
| 55 | if (!ns) |
| 56 | SMC_RET1(handle, SMC_UNK); |
| 57 | |
Kalyani Chidambaram Vaidyanathan | 1b3fa45 | 2023-01-30 17:44:26 -0800 | [diff] [blame] | 58 | if ((smc_fid == TEGRA_SIP_PMC_COMMANDS) || (smc_fid == TEGRA_SIP_PMC_COMMANDS_LEGACY)) { |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 59 | /* check the address is within PMC range and is 4byte aligned */ |
| 60 | if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) |
| 61 | return -EINVAL; |
| 62 | |
kalyani chidambaram | ca4e497 | 2018-06-19 13:34:39 -0700 | [diff] [blame] | 63 | switch (x2) { |
| 64 | /* Black listed PMC registers */ |
| 65 | case PMC_SCRATCH1: |
| 66 | case PMC_SCRATCH31 ... PMC_SCRATCH33: |
| 67 | case PMC_SCRATCH40: |
| 68 | case PMC_SCRATCH42: |
| 69 | case PMC_SCRATCH43 ... PMC_SCRATCH48: |
| 70 | case PMC_SCRATCH50 ... PMC_SCRATCH51: |
| 71 | case PMC_SCRATCH56 ... PMC_SCRATCH57: |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 72 | /* PMC secure-only registers are not accessible */ |
kalyani chidambaram | ca4e497 | 2018-06-19 13:34:39 -0700 | [diff] [blame] | 73 | case PMC_DPD_ENABLE_0: |
| 74 | case PMC_FUSE_CONTROL_0: |
| 75 | case PMC_CRYPTO_OP_0: |
| 76 | case PMC_TSC_MULT_0: |
| 77 | case PMC_STICKY_BIT: |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 78 | ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 79 | return -EFAULT; |
kalyani chidambaram | ca4e497 | 2018-06-19 13:34:39 -0700 | [diff] [blame] | 80 | default: |
| 81 | /* Valid register */ |
| 82 | break; |
| 83 | } |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 84 | |
| 85 | /* Perform PMC read/write */ |
| 86 | if (x1 == PMC_READ) { |
| 87 | val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); |
| 88 | write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val); |
| 89 | } else if (x1 == PMC_WRITE) { |
| 90 | mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); |
| 91 | } else { |
| 92 | return -EINVAL; |
| 93 | } |
kalyani chidambaram | ca4e497 | 2018-06-19 13:34:39 -0700 | [diff] [blame] | 94 | } else { |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 95 | return -ENOTSUP; |
| 96 | } |
kalyani chidambaram | a1ad9b7 | 2018-03-06 16:36:57 -0800 | [diff] [blame] | 97 | return 0; |
| 98 | } |