Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2019-2020, Broadcom |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 7 | # Set the toc_flags to 1 for 100% speed operation |
| 8 | # Set the toc_flags to 2 for 50% speed operation |
| 9 | # Set the toc_flags to 3 for 25% speed operation |
| 10 | # Set the toc_flags bit 3 to indicate ignore the fip in UEFI copy mode |
| 11 | PLAT_TOC_FLAGS := 0x0 |
| 12 | |
| 13 | # Set the IHOST_PLL_FREQ to, |
| 14 | # 1 for full speed |
| 15 | # 2 for 50% speed |
| 16 | # 3 for 25% speed |
| 17 | # 0 for bypass |
| 18 | $(eval $(call add_define_val,IHOST_PLL_FREQ,1)) |
| 19 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 20 | # Enable workaround for ERRATA_A72_859971 |
| 21 | ERRATA_A72_859971 := 1 |
| 22 | |
| 23 | # Cache Coherency Interconnect Driver needed |
| 24 | DRIVER_CC_ENABLE := 1 |
| 25 | $(eval $(call add_define,DRIVER_CC_ENABLE)) |
| 26 | |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 27 | # BL31 is in DRAM |
| 28 | ARM_BL31_IN_DRAM := 1 |
| 29 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 30 | USE_CRMU_SRAM := yes |
| 31 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 32 | # Enable error logging by default for Stingray |
| 33 | BCM_ELOG := yes |
| 34 | |
| 35 | # Enable FRU support by default for Stingray |
| 36 | ifeq (${USE_FRU},) |
| 37 | USE_FRU := no |
| 38 | endif |
| 39 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 40 | # Use single cluster |
| 41 | ifeq (${USE_SINGLE_CLUSTER},yes) |
| 42 | $(info Using Single Cluster) |
| 43 | $(eval $(call add_define,USE_SINGLE_CLUSTER)) |
| 44 | endif |
| 45 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 46 | # Use DDR |
| 47 | ifeq (${USE_DDR},yes) |
| 48 | $(info Using DDR) |
| 49 | $(eval $(call add_define,USE_DDR)) |
| 50 | endif |
| 51 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 52 | ifeq (${BOARD_CFG},) |
| 53 | BOARD_CFG := bcm958742k |
| 54 | endif |
| 55 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 56 | # Use NAND |
| 57 | ifeq (${USE_NAND},$(filter yes, ${USE_NAND})) |
| 58 | $(info Using NAND) |
| 59 | $(eval $(call add_define,USE_NAND)) |
| 60 | endif |
| 61 | |
| 62 | # Enable Broadcom error logging support |
| 63 | ifeq (${BCM_ELOG},yes) |
| 64 | $(info Using BCM_ELOG) |
| 65 | $(eval $(call add_define,BCM_ELOG)) |
| 66 | endif |
| 67 | |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 68 | # BL31 build for standalone mode |
| 69 | ifeq (${STANDALONE_BL31},yes) |
| 70 | RESET_TO_BL31 := 1 |
| 71 | $(info Using RESET_TO_BL31) |
| 72 | endif |
| 73 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 74 | # For testing purposes, use memsys stubs. Remove once memsys is fully tested. |
| 75 | USE_MEMSYS_STUBS := yes |
| 76 | |
| 77 | # Default, use BL1_RW area |
| 78 | ifneq (${BL2_USE_BL1_RW},no) |
| 79 | $(eval $(call add_define,USE_BL1_RW)) |
| 80 | endif |
| 81 | |
| 82 | # Default soft reset is L3 |
| 83 | $(eval $(call add_define,CONFIG_SOFT_RESET_L3)) |
| 84 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 85 | # Enable Chip OTP driver |
| 86 | DRIVER_OCOTP_ENABLE := 1 |
| 87 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 88 | include plat/brcm/board/common/board_common.mk |
| 89 | |
| 90 | SOC_DIR := brcm/board/stingray |
| 91 | |
| 92 | PLAT_INCLUDES += -Iplat/${SOC_DIR}/include/ \ |
| 93 | -Iinclude/plat/brcm/common/ \ |
| 94 | -Iplat/brcm/common/ |
| 95 | |
| 96 | PLAT_BL_COMMON_SOURCES += lib/cpus/aarch64/cortex_a72.S \ |
| 97 | plat/${SOC_DIR}/aarch64/plat_helpers.S \ |
| 98 | drivers/ti/uart/aarch64/16550_console.S \ |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 99 | plat/${SOC_DIR}/src/tz_sec.c \ |
| 100 | drivers/arm/tzc/tzc400.c \ |
| 101 | plat/${SOC_DIR}/src/topology.c |
| 102 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 103 | BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \ |
| 104 | plat/${SOC_DIR}/src/bl2_setup.c \ |
| 105 | plat/${SOC_DIR}/driver/swreg.c |
| 106 | |
| 107 | |
| 108 | ifeq (${USE_DDR},yes) |
| 109 | PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include |
| 110 | else |
| 111 | PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ext_sram_init |
| 112 | BL2_SOURCES += plat/${SOC_DIR}/driver/ext_sram_init/ext_sram_init.c |
| 113 | endif |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 114 | |
| 115 | # Include GICv3 driver files |
| 116 | include drivers/arm/gic/v3/gicv3.mk |
| 117 | |
| 118 | BRCM_GIC_SOURCES := ${GICV3_SOURCES} \ |
| 119 | plat/common/plat_gicv3.c \ |
| 120 | plat/brcm/common/brcm_gicv3.c |
| 121 | |
| 122 | BL31_SOURCES += \ |
| 123 | drivers/arm/ccn/ccn.c \ |
| 124 | plat/brcm/board/common/timer_sync.c \ |
| 125 | plat/brcm/common/brcm_ccn.c \ |
| 126 | plat/common/plat_psci_common.c \ |
| 127 | plat/${SOC_DIR}/driver/ihost_pll_config.c \ |
| 128 | ${BRCM_GIC_SOURCES} |
| 129 | |
| 130 | ifdef SCP_BL2 |
| 131 | PLAT_INCLUDES += -Iplat/brcm/common/ |
| 132 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 133 | BL2_SOURCES += plat/brcm/common/brcm_mhu.c \ |
| 134 | plat/brcm/common/brcm_scpi.c \ |
| 135 | plat/${SOC_DIR}/src/scp_utils.c \ |
| 136 | plat/${SOC_DIR}/src/scp_cmd.c \ |
| 137 | drivers/brcm/scp.c |
| 138 | |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 139 | BL31_SOURCES += plat/brcm/common/brcm_mhu.c \ |
| 140 | plat/brcm/common/brcm_scpi.c \ |
| 141 | plat/${SOC_DIR}/src/brcm_pm_ops.c |
| 142 | else |
| 143 | BL31_SOURCES += plat/${SOC_DIR}/src/ihost_pm.c \ |
| 144 | plat/${SOC_DIR}/src/pm.c |
| 145 | endif |
| 146 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 147 | ifeq (${ELOG_SUPPORT},1) |
| 148 | ifeq (${ELOG_STORE_MEDIA},DDR) |
| 149 | BL2_SOURCES += plat/brcm/board/common/bcm_elog_ddr.c |
| 150 | endif |
| 151 | endif |
| 152 | |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 153 | # Do not execute the startup code on warm reset. |
| 154 | PROGRAMMABLE_RESET_ADDRESS := 1 |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame^] | 155 | |
| 156 | # Nitro FW, config and Crash log uses secure DDR memory |
| 157 | # Inaddition to above, Nitro master and slave is also secure |
| 158 | ifneq ($(NITRO_SECURE_ACCESS),) |
| 159 | $(eval $(call add_define,NITRO_SECURE_ACCESS)) |
| 160 | $(eval $(call add_define,DDR_NITRO_SECURE_REGION_START)) |
| 161 | $(eval $(call add_define,DDR_NITRO_SECURE_REGION_END)) |
| 162 | endif |