blob: b1054db2291f9a62e462882eb1f1396d068da455 [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#ifndef __BOARD_MARVELL_DEF_H__
9#define __BOARD_MARVELL_DEF_H__
10
11/*
12 * Required platform porting definitions common to all ARM
13 * development platforms
14 */
15
16/* Size of cacheable stacks */
17#if DEBUG_XLAT_TABLE
18# define PLATFORM_STACK_SIZE 0x800
19#elif IMAGE_BL1
20#if TRUSTED_BOARD_BOOT
21# define PLATFORM_STACK_SIZE 0x1000
22#else
23# define PLATFORM_STACK_SIZE 0x440
24#endif
25#elif IMAGE_BL2
26# if TRUSTED_BOARD_BOOT
27# define PLATFORM_STACK_SIZE 0x1000
28# else
29# define PLATFORM_STACK_SIZE 0x400
30# endif
31#elif IMAGE_BL31
32# define PLATFORM_STACK_SIZE 0x400
33#elif IMAGE_BL32
34# define PLATFORM_STACK_SIZE 0x440
35#endif
36
37/*
38 * PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the
39 * plat_arm_mmap array defined for each BL stage.
40 */
41#if IMAGE_BLE
42# define PLAT_MARVELL_MMAP_ENTRIES 3
43#endif
44#if IMAGE_BL1
45# if TRUSTED_BOARD_BOOT
46# define PLAT_MARVELL_MMAP_ENTRIES 7
47# else
48# define PLAT_MARVELL_MMAP_ENTRIES 6
49# endif /* TRUSTED_BOARD_BOOT */
50#endif
51#if IMAGE_BL2
52# define PLAT_MARVELL_MMAP_ENTRIES 8
53#endif
54#if IMAGE_BL31
55#define PLAT_MARVELL_MMAP_ENTRIES 5
56#endif
57
58/*
59 * Platform specific page table and MMU setup constants
60 */
61#if IMAGE_BL1
62#define MAX_XLAT_TABLES 4
63#elif IMAGE_BLE
64# define MAX_XLAT_TABLES 4
65#elif IMAGE_BL2
66# define MAX_XLAT_TABLES 4
67#elif IMAGE_BL31
68# define MAX_XLAT_TABLES 4
69#elif IMAGE_BL32
70# define MAX_XLAT_TABLES 4
71#endif
72
73#define MAX_IO_DEVICES 3
74#define MAX_IO_HANDLES 4
75
76#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */
77
78
79#endif /* __BOARD_MARVELL_DEF_H__ */