Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2016, Renesas Electronics Corporation |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> |
| 9 | #include "boot_init_dram.h" |
| 10 | #include "boot_init_dram_regdef_v3m.h" |
| 11 | |
| 12 | static void WriteReg_32(uintptr_t a, uint32_t v) |
| 13 | { |
| 14 | *(volatile uint32_t*)a = v; |
| 15 | } |
| 16 | |
| 17 | static uint32_t ReadReg_32(uintptr_t a) |
| 18 | { |
| 19 | uint32_t w = *(volatile uint32_t*)a; |
| 20 | return w; |
| 21 | } |
| 22 | |
| 23 | static uint32_t init_ddr_v3m_1600(void) |
| 24 | { |
| 25 | // last modified 2016.12.16 |
| 26 | |
| 27 | uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; |
| 28 | |
| 29 | WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); |
| 30 | WriteReg_32(DBSC_V3M_DBKIND,0x00000007); |
| 31 | #if RCAR_DRAM_DDR3L_MEMCONF == 0 |
| 32 | WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle |
| 33 | #else |
| 34 | WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK |
| 35 | #endif |
| 36 | WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); |
| 37 | WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); |
| 38 | WriteReg_32(DBSC_V3M_DBTR1,0x00000008); |
| 39 | WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); |
| 40 | WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); |
| 41 | WriteReg_32(DBSC_V3M_DBTR5,0x00000027); |
| 42 | WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); |
| 43 | WriteReg_32(DBSC_V3M_DBTR7,0x00060006); |
| 44 | WriteReg_32(DBSC_V3M_DBTR8,0x00000020); |
| 45 | WriteReg_32(DBSC_V3M_DBTR9,0x00000006); |
| 46 | WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); |
| 47 | WriteReg_32(DBSC_V3M_DBTR11,0x0000000B); |
| 48 | WriteReg_32(DBSC_V3M_DBTR12,0x00120012); |
| 49 | WriteReg_32(DBSC_V3M_DBTR13,0x01180118); |
| 50 | WriteReg_32(DBSC_V3M_DBTR14,0x00140005); |
| 51 | WriteReg_32(DBSC_V3M_DBTR15,0x00050004); |
| 52 | WriteReg_32(DBSC_V3M_DBTR16,0x071D0305); |
| 53 | WriteReg_32(DBSC_V3M_DBTR17,0x040C0010); |
| 54 | WriteReg_32(DBSC_V3M_DBTR18,0x00000200); |
| 55 | WriteReg_32(DBSC_V3M_DBTR19,0x01000040); |
| 56 | WriteReg_32(DBSC_V3M_DBTR20,0x02000120); |
| 57 | WriteReg_32(DBSC_V3M_DBTR21,0x00040004); |
| 58 | WriteReg_32(DBSC_V3M_DBBL,0x00000000); |
| 59 | WriteReg_32(DBSC_V3M_DBODT0,0x00000001); |
| 60 | WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); |
| 61 | WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010); |
| 62 | WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000); |
| 63 | WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f); |
| 64 | WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010); |
| 65 | WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); |
| 66 | WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200); |
| 67 | WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040); |
| 68 | WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600); |
| 69 | WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480); |
| 70 | WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300); |
| 71 | WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180); |
| 72 | WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400); |
| 73 | WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300); |
| 74 | WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); |
| 75 | WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); |
| 76 | WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300); |
| 77 | WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240); |
| 78 | WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180); |
| 79 | WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0); |
| 80 | WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200); |
| 81 | WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180); |
| 82 | WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100); |
| 83 | WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080); |
| 84 | WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100); |
| 85 | WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0); |
| 86 | WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080); |
| 87 | WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040); |
| 88 | WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); |
| 89 | WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04); |
| 90 | WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4); |
| 91 | WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003); |
| 92 | WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080); |
| 93 | WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); |
| 94 | |
| 95 | WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); |
| 96 | WriteReg_32(DBSC_V3M_DBCMD,0x01000001); |
| 97 | WriteReg_32(DBSC_V3M_DBCMD,0x08000000); |
| 98 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 99 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); |
| 100 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 101 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 102 | |
| 103 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); |
| 104 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); |
| 105 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); |
| 106 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); |
| 107 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); |
| 108 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); |
| 109 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); |
| 110 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); |
| 111 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); |
| 112 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); |
| 113 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); |
| 114 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); |
| 115 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); |
| 116 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); |
| 117 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 118 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); |
| 119 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 120 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 121 | |
| 122 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); |
| 123 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); |
| 124 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); |
| 125 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); |
| 126 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 127 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 128 | |
| 129 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); |
| 130 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700); |
| 131 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); |
| 132 | while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 133 | |
| 134 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); |
| 135 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170); |
| 136 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); |
| 137 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); |
| 138 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); |
| 139 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); |
| 140 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); |
| 141 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400); |
| 142 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); |
| 143 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200); |
| 144 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); |
| 145 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); |
| 146 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); |
| 147 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); |
| 148 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); |
| 149 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); |
| 150 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); |
| 151 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); |
| 152 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); |
| 153 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); |
| 154 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); |
| 155 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); |
| 156 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); |
| 157 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10); |
| 158 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 159 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 160 | |
| 161 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); |
| 162 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 163 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); |
| 164 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 165 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); |
| 166 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); |
| 167 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); |
| 168 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 169 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); |
| 170 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 171 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); |
| 172 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); |
| 173 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); |
| 174 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 175 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); |
| 176 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 177 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); |
| 178 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); |
| 179 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); |
| 180 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 181 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); |
| 182 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); |
| 183 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); |
| 184 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); |
| 185 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 186 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); |
| 187 | WriteReg_32(DBSC_V3M_DBCMD,0x08000001); |
| 188 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 189 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 190 | |
| 191 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 192 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); |
| 193 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 194 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 195 | |
| 196 | for (uint32_t i = 0; i<4; i++) |
| 197 | { |
| 198 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); |
| 199 | RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; |
| 200 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); |
| 201 | RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; |
| 202 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); |
| 203 | RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; |
| 204 | if ( RegVal_R6 > 0 ) |
| 205 | { |
| 206 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); |
| 207 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; |
| 208 | |
| 209 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); |
| 210 | WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); |
| 211 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); |
| 212 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; |
| 213 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); |
| 214 | WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); |
| 215 | } else { |
| 216 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); |
| 217 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; |
| 218 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); |
| 219 | WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); |
| 220 | |
| 221 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); |
| 222 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; |
| 223 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); |
| 224 | WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); |
| 229 | WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); |
| 230 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); |
| 231 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 232 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); |
| 233 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 234 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); |
| 235 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 236 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); |
| 237 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 238 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 239 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); |
| 240 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 241 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 242 | |
| 243 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); |
| 244 | WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); |
| 245 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 246 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); |
| 247 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 248 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 249 | |
| 250 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); |
| 251 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); |
| 252 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); |
| 253 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); |
| 254 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); |
| 255 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); |
| 256 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); |
| 257 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); |
| 258 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); |
| 259 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); |
| 260 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 261 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); |
| 262 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 263 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 264 | |
| 265 | for (uint32_t i = 0; i < 4; i++) |
| 266 | { |
| 267 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); |
| 268 | RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; |
| 269 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); |
| 270 | RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); |
| 271 | |
| 272 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); |
| 273 | RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); |
| 274 | RegVal_R12 = (RegVal_R5 >> 2); |
| 275 | if (RegVal_R6 - RegVal_R12 > 0) |
| 276 | { |
| 277 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); |
| 278 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); |
| 279 | |
| 280 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); |
| 281 | WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); |
| 282 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); |
| 283 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); |
| 284 | |
| 285 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); |
| 286 | WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); |
| 287 | } |
| 288 | else |
| 289 | { |
| 290 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); |
| 291 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); |
| 292 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); |
| 293 | WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); |
| 294 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); |
| 295 | RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); |
| 296 | WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); |
| 297 | WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); |
| 298 | } |
| 299 | } |
| 300 | |
| 301 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); |
| 302 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 303 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); |
| 304 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 305 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); |
| 306 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 307 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); |
| 308 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); |
| 309 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); |
| 310 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); |
| 311 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); |
| 312 | while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); |
| 313 | |
| 314 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); |
| 315 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700); |
| 316 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); |
| 317 | while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); |
| 318 | WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); |
| 319 | WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); |
| 320 | |
| 321 | WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); |
| 322 | WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001); |
| 323 | WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E); |
| 324 | WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860); |
| 325 | WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); |
| 326 | WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); |
| 327 | WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); |
| 328 | WriteReg_32(DBSC_V3M_DBACEN,0x00000001); |
| 329 | WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); |
| 330 | WriteReg_32(0xE67F0024, 0x00000001); |
| 331 | WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); |
| 332 | |
| 333 | return 1; |
| 334 | } |
| 335 | |
| 336 | int32_t rcar_dram_init(void) |
| 337 | { |
| 338 | return init_ddr_v3m_1600() ? INITDRAM_OK : INITDRAM_NG; |
| 339 | } |