Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 10 | #include <cortex_a57.h> |
| 11 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable intra-cluster coherency |
| 15 | * Clobbers: r0-r1 |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 19 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 20 | bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 21 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 22 | bx lr |
| 23 | endfunc cortex_a57_disable_smp |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable all types of L2 prefetches. |
| 27 | * Clobbers: r0-r2 |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 31 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 32 | orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 33 | bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ |
| 34 | CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) |
| 35 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 36 | isb |
| 37 | dsb ish |
| 38 | bx lr |
| 39 | endfunc cortex_a57_disable_l2_prefetch |
| 40 | |
| 41 | /* --------------------------------------------- |
| 42 | * Disable debug interfaces |
| 43 | * --------------------------------------------- |
| 44 | */ |
| 45 | func cortex_a57_disable_ext_debug |
| 46 | mov r0, #1 |
| 47 | stcopr r0, DBGOSDLR |
| 48 | isb |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 49 | #if ERRATA_A57_817169 |
| 50 | /* |
| 51 | * Invalidate any TLB address |
| 52 | */ |
| 53 | mov r0, #0 |
| 54 | stcopr r0, TLBIMVA |
| 55 | #endif |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 56 | dsb sy |
| 57 | bx lr |
| 58 | endfunc cortex_a57_disable_ext_debug |
| 59 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 60 | /* -------------------------------------------------- |
| 61 | * Errata Workaround for Cortex A57 Errata #806969. |
| 62 | * This applies only to revision r0p0 of Cortex A57. |
| 63 | * Inputs: |
| 64 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 65 | * Shall clobber: r0-r3 |
| 66 | * -------------------------------------------------- |
| 67 | */ |
| 68 | func errata_a57_806969_wa |
| 69 | /* |
| 70 | * Compare r0 against revision r0p0 |
| 71 | */ |
| 72 | mov r2, lr |
| 73 | bl check_errata_806969 |
| 74 | mov lr, r2 |
| 75 | cmp r0, #ERRATA_NOT_APPLIES |
| 76 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 77 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 78 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 79 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 80 | 1: |
| 81 | bx lr |
| 82 | endfunc errata_a57_806969_wa |
| 83 | |
| 84 | func check_errata_806969 |
| 85 | mov r1, #0x00 |
| 86 | b cpu_rev_var_ls |
| 87 | endfunc check_errata_806969 |
| 88 | |
| 89 | /* --------------------------------------------------- |
| 90 | * Errata Workaround for Cortex A57 Errata #813419. |
| 91 | * This applies only to revision r0p0 of Cortex A57. |
| 92 | * --------------------------------------------------- |
| 93 | */ |
| 94 | func check_errata_813419 |
| 95 | /* |
| 96 | * Even though this is only needed for revision r0p0, it |
| 97 | * is always applied due to limitations of the current |
| 98 | * errata framework. |
| 99 | */ |
| 100 | mov r0, #ERRATA_APPLIES |
| 101 | bx lr |
| 102 | endfunc check_errata_813419 |
| 103 | |
| 104 | /* --------------------------------------------------- |
| 105 | * Errata Workaround for Cortex A57 Errata #813420. |
| 106 | * This applies only to revision r0p0 of Cortex A57. |
| 107 | * Inputs: |
| 108 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 109 | * Shall clobber: r0-r3 |
| 110 | * --------------------------------------------------- |
| 111 | */ |
| 112 | func errata_a57_813420_wa |
| 113 | /* |
| 114 | * Compare r0 against revision r0p0 |
| 115 | */ |
| 116 | mov r2, lr |
| 117 | bl check_errata_813420 |
| 118 | mov lr, r2 |
| 119 | cmp r0, #ERRATA_NOT_APPLIES |
| 120 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 121 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 122 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI |
| 123 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 124 | 1: |
| 125 | bx lr |
| 126 | endfunc errata_a57_813420_wa |
| 127 | |
| 128 | func check_errata_813420 |
| 129 | mov r1, #0x00 |
| 130 | b cpu_rev_var_ls |
| 131 | endfunc check_errata_813420 |
| 132 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 133 | /* --------------------------------------------------- |
| 134 | * Errata Workaround for Cortex A57 Errata #814670. |
| 135 | * This applies only to revision r0p0 of Cortex A57. |
| 136 | * Inputs: |
| 137 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 138 | * Shall clobber: r0-r3 |
| 139 | * --------------------------------------------------- |
| 140 | */ |
| 141 | func errata_a57_814670_wa |
| 142 | /* |
| 143 | * Compare r0 against revision r0p0 |
| 144 | */ |
| 145 | mov r2, lr |
| 146 | bl check_errata_814670 |
| 147 | cmp r0, #ERRATA_NOT_APPLIES |
| 148 | beq 1f |
| 149 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 150 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION |
| 151 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 152 | isb |
| 153 | 1: |
| 154 | bx r2 |
| 155 | endfunc errata_a57_814670_wa |
| 156 | |
| 157 | func check_errata_814670 |
| 158 | mov r1, #0x00 |
| 159 | b cpu_rev_var_ls |
| 160 | endfunc check_errata_814670 |
| 161 | |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 162 | /* ---------------------------------------------------- |
| 163 | * Errata Workaround for Cortex A57 Errata #817169. |
| 164 | * This applies only to revision <= r0p1 of Cortex A57. |
| 165 | * ---------------------------------------------------- |
| 166 | */ |
| 167 | func check_errata_817169 |
| 168 | /* |
| 169 | * Even though this is only needed for revision <= r0p1, it |
| 170 | * is always applied because of the low cost of the workaround. |
| 171 | */ |
| 172 | mov r0, #ERRATA_APPLIES |
| 173 | bx lr |
| 174 | endfunc check_errata_817169 |
| 175 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 176 | /* -------------------------------------------------------------------- |
| 177 | * Disable the over-read from the LDNP instruction. |
| 178 | * |
| 179 | * This applies to all revisions <= r1p2. The performance degradation |
| 180 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 181 | * |
| 182 | * Inputs: |
| 183 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 184 | * Shall clobber: r0-r3 |
| 185 | * --------------------------------------------------------------------- |
| 186 | */ |
| 187 | func a57_disable_ldnp_overread |
| 188 | /* |
| 189 | * Compare r0 against revision r1p2 |
| 190 | */ |
| 191 | mov r2, lr |
| 192 | bl check_errata_disable_ldnp_overread |
| 193 | mov lr, r2 |
| 194 | cmp r0, #ERRATA_NOT_APPLIES |
| 195 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 196 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 197 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD |
| 198 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 199 | 1: |
| 200 | bx lr |
| 201 | endfunc a57_disable_ldnp_overread |
| 202 | |
| 203 | func check_errata_disable_ldnp_overread |
| 204 | mov r1, #0x12 |
| 205 | b cpu_rev_var_ls |
| 206 | endfunc check_errata_disable_ldnp_overread |
| 207 | |
| 208 | /* --------------------------------------------------- |
| 209 | * Errata Workaround for Cortex A57 Errata #826974. |
| 210 | * This applies only to revision <= r1p1 of Cortex A57. |
| 211 | * Inputs: |
| 212 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 213 | * Shall clobber: r0-r3 |
| 214 | * --------------------------------------------------- |
| 215 | */ |
| 216 | func errata_a57_826974_wa |
| 217 | /* |
| 218 | * Compare r0 against revision r1p1 |
| 219 | */ |
| 220 | mov r2, lr |
| 221 | bl check_errata_826974 |
| 222 | mov lr, r2 |
| 223 | cmp r0, #ERRATA_NOT_APPLIES |
| 224 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 225 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 226 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB |
| 227 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 228 | 1: |
| 229 | bx lr |
| 230 | endfunc errata_a57_826974_wa |
| 231 | |
| 232 | func check_errata_826974 |
| 233 | mov r1, #0x11 |
| 234 | b cpu_rev_var_ls |
| 235 | endfunc check_errata_826974 |
| 236 | |
| 237 | /* --------------------------------------------------- |
| 238 | * Errata Workaround for Cortex A57 Errata #826977. |
| 239 | * This applies only to revision <= r1p1 of Cortex A57. |
| 240 | * Inputs: |
| 241 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 242 | * Shall clobber: r0-r3 |
| 243 | * --------------------------------------------------- |
| 244 | */ |
| 245 | func errata_a57_826977_wa |
| 246 | /* |
| 247 | * Compare r0 against revision r1p1 |
| 248 | */ |
| 249 | mov r2, lr |
| 250 | bl check_errata_826977 |
| 251 | mov lr, r2 |
| 252 | cmp r0, #ERRATA_NOT_APPLIES |
| 253 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 254 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 255 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE |
| 256 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 257 | 1: |
| 258 | bx lr |
| 259 | endfunc errata_a57_826977_wa |
| 260 | |
| 261 | func check_errata_826977 |
| 262 | mov r1, #0x11 |
| 263 | b cpu_rev_var_ls |
| 264 | endfunc check_errata_826977 |
| 265 | |
| 266 | /* --------------------------------------------------- |
| 267 | * Errata Workaround for Cortex A57 Errata #828024. |
| 268 | * This applies only to revision <= r1p1 of Cortex A57. |
| 269 | * Inputs: |
| 270 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 271 | * Shall clobber: r0-r3 |
| 272 | * --------------------------------------------------- |
| 273 | */ |
| 274 | func errata_a57_828024_wa |
| 275 | /* |
| 276 | * Compare r0 against revision r1p1 |
| 277 | */ |
| 278 | mov r2, lr |
| 279 | bl check_errata_828024 |
| 280 | mov lr, r2 |
| 281 | cmp r0, #ERRATA_NOT_APPLIES |
| 282 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 283 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 284 | /* |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 285 | * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 286 | * instructions here because the resulting bitmask doesn't fit in a |
| 287 | * 16-bit value so it cannot be encoded in a single instruction. |
| 288 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 289 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA |
| 290 | orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING) |
| 291 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 292 | 1: |
| 293 | bx lr |
| 294 | endfunc errata_a57_828024_wa |
| 295 | |
| 296 | func check_errata_828024 |
| 297 | mov r1, #0x11 |
| 298 | b cpu_rev_var_ls |
| 299 | endfunc check_errata_828024 |
| 300 | |
| 301 | /* --------------------------------------------------- |
| 302 | * Errata Workaround for Cortex A57 Errata #829520. |
| 303 | * This applies only to revision <= r1p2 of Cortex A57. |
| 304 | * Inputs: |
| 305 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 306 | * Shall clobber: r0-r3 |
| 307 | * --------------------------------------------------- |
| 308 | */ |
| 309 | func errata_a57_829520_wa |
| 310 | /* |
| 311 | * Compare r0 against revision r1p2 |
| 312 | */ |
| 313 | mov r2, lr |
| 314 | bl check_errata_829520 |
| 315 | mov lr, r2 |
| 316 | cmp r0, #ERRATA_NOT_APPLIES |
| 317 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 318 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 319 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 320 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 321 | 1: |
| 322 | bx lr |
| 323 | endfunc errata_a57_829520_wa |
| 324 | |
| 325 | func check_errata_829520 |
| 326 | mov r1, #0x12 |
| 327 | b cpu_rev_var_ls |
| 328 | endfunc check_errata_829520 |
| 329 | |
| 330 | /* --------------------------------------------------- |
| 331 | * Errata Workaround for Cortex A57 Errata #833471. |
| 332 | * This applies only to revision <= r1p2 of Cortex A57. |
| 333 | * Inputs: |
| 334 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 335 | * Shall clobber: r0-r3 |
| 336 | * --------------------------------------------------- |
| 337 | */ |
| 338 | func errata_a57_833471_wa |
| 339 | /* |
| 340 | * Compare r0 against revision r1p2 |
| 341 | */ |
| 342 | mov r2, lr |
| 343 | bl check_errata_833471 |
| 344 | mov lr, r2 |
| 345 | cmp r0, #ERRATA_NOT_APPLIES |
| 346 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 347 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 348 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH |
| 349 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 350 | 1: |
| 351 | bx lr |
| 352 | endfunc errata_a57_833471_wa |
| 353 | |
| 354 | func check_errata_833471 |
| 355 | mov r1, #0x12 |
| 356 | b cpu_rev_var_ls |
| 357 | endfunc check_errata_833471 |
| 358 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 359 | /* --------------------------------------------------- |
| 360 | * Errata Workaround for Cortex A57 Errata #859972. |
| 361 | * This applies only to revision <= r1p3 of Cortex A57. |
| 362 | * Inputs: |
| 363 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 364 | * Shall clobber: r0-r3 |
| 365 | * --------------------------------------------------- |
| 366 | */ |
| 367 | func errata_a57_859972_wa |
| 368 | mov r2, lr |
| 369 | bl check_errata_859972 |
| 370 | mov lr, r2 |
| 371 | cmp r0, #ERRATA_NOT_APPLIES |
| 372 | beq 1f |
| 373 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 374 | orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH |
| 375 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 376 | 1: |
| 377 | bx lr |
| 378 | endfunc errata_a57_859972_wa |
| 379 | |
| 380 | func check_errata_859972 |
| 381 | mov r1, #0x13 |
| 382 | b cpu_rev_var_ls |
| 383 | endfunc check_errata_859972 |
| 384 | |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 385 | func check_errata_cve_2017_5715 |
| 386 | mov r0, #ERRATA_MISSING |
| 387 | bx lr |
| 388 | endfunc check_errata_cve_2017_5715 |
| 389 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 390 | func check_errata_cve_2018_3639 |
| 391 | #if WORKAROUND_CVE_2018_3639 |
| 392 | mov r0, #ERRATA_APPLIES |
| 393 | #else |
| 394 | mov r0, #ERRATA_MISSING |
| 395 | #endif |
| 396 | bx lr |
| 397 | endfunc check_errata_cve_2018_3639 |
| 398 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 399 | /* ------------------------------------------------- |
| 400 | * The CPU Ops reset function for Cortex-A57. |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 401 | * Shall clobber: r0-r6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 402 | * ------------------------------------------------- |
| 403 | */ |
| 404 | func cortex_a57_reset_func |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 405 | mov r5, lr |
| 406 | bl cpu_get_rev_var |
| 407 | mov r4, r0 |
| 408 | |
| 409 | #if ERRATA_A57_806969 |
| 410 | mov r0, r4 |
| 411 | bl errata_a57_806969_wa |
| 412 | #endif |
| 413 | |
| 414 | #if ERRATA_A57_813420 |
| 415 | mov r0, r4 |
| 416 | bl errata_a57_813420_wa |
| 417 | #endif |
| 418 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 419 | #if ERRATA_A57_814670 |
| 420 | mov r0, r4 |
| 421 | bl errata_a57_814670_wa |
| 422 | #endif |
| 423 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 424 | #if A57_DISABLE_NON_TEMPORAL_HINT |
| 425 | mov r0, r4 |
| 426 | bl a57_disable_ldnp_overread |
| 427 | #endif |
| 428 | |
| 429 | #if ERRATA_A57_826974 |
| 430 | mov r0, r4 |
| 431 | bl errata_a57_826974_wa |
| 432 | #endif |
| 433 | |
| 434 | #if ERRATA_A57_826977 |
| 435 | mov r0, r4 |
| 436 | bl errata_a57_826977_wa |
| 437 | #endif |
| 438 | |
| 439 | #if ERRATA_A57_828024 |
| 440 | mov r0, r4 |
| 441 | bl errata_a57_828024_wa |
| 442 | #endif |
| 443 | |
| 444 | #if ERRATA_A57_829520 |
| 445 | mov r0, r4 |
| 446 | bl errata_a57_829520_wa |
| 447 | #endif |
| 448 | |
| 449 | #if ERRATA_A57_833471 |
| 450 | mov r0, r4 |
| 451 | bl errata_a57_833471_wa |
| 452 | #endif |
| 453 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 454 | #if ERRATA_A57_859972 |
| 455 | mov r0, r4 |
| 456 | bl errata_a57_859972_wa |
| 457 | #endif |
| 458 | |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 459 | #if WORKAROUND_CVE_2018_3639 |
| 460 | ldcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 461 | orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE |
| 462 | stcopr16 r0, r1, CORTEX_A57_CPUACTLR |
| 463 | isb |
| 464 | dsb sy |
| 465 | #endif |
| 466 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 467 | /* --------------------------------------------- |
| 468 | * Enable the SMP bit. |
| 469 | * --------------------------------------------- |
| 470 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 471 | ldcopr16 r0, r1, CORTEX_A57_ECTLR |
| 472 | orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT |
| 473 | stcopr16 r0, r1, CORTEX_A57_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 474 | isb |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 475 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 476 | endfunc cortex_a57_reset_func |
| 477 | |
| 478 | /* ---------------------------------------------------- |
| 479 | * The CPU Ops core power down function for Cortex-A57. |
| 480 | * ---------------------------------------------------- |
| 481 | */ |
| 482 | func cortex_a57_core_pwr_dwn |
| 483 | push {r12, lr} |
| 484 | |
| 485 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 486 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 487 | ldcopr r0, SCTLR |
| 488 | tst r0, #SCTLR_C_BIT |
| 489 | ASM_ASSERT(eq) |
| 490 | #endif |
| 491 | |
| 492 | /* --------------------------------------------- |
| 493 | * Disable the L2 prefetches. |
| 494 | * --------------------------------------------- |
| 495 | */ |
| 496 | bl cortex_a57_disable_l2_prefetch |
| 497 | |
| 498 | /* --------------------------------------------- |
| 499 | * Flush L1 caches. |
| 500 | * --------------------------------------------- |
| 501 | */ |
| 502 | mov r0, #DC_OP_CISW |
| 503 | bl dcsw_op_level1 |
| 504 | |
| 505 | /* --------------------------------------------- |
| 506 | * Come out of intra cluster coherency |
| 507 | * --------------------------------------------- |
| 508 | */ |
| 509 | bl cortex_a57_disable_smp |
| 510 | |
| 511 | /* --------------------------------------------- |
| 512 | * Force the debug interfaces to be quiescent |
| 513 | * --------------------------------------------- |
| 514 | */ |
| 515 | pop {r12, lr} |
| 516 | b cortex_a57_disable_ext_debug |
| 517 | endfunc cortex_a57_core_pwr_dwn |
| 518 | |
| 519 | /* ------------------------------------------------------- |
| 520 | * The CPU Ops cluster power down function for Cortex-A57. |
| 521 | * Clobbers: r0-r3 |
| 522 | * ------------------------------------------------------- |
| 523 | */ |
| 524 | func cortex_a57_cluster_pwr_dwn |
| 525 | push {r12, lr} |
| 526 | |
| 527 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 528 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 529 | ldcopr r0, SCTLR |
| 530 | tst r0, #SCTLR_C_BIT |
| 531 | ASM_ASSERT(eq) |
| 532 | #endif |
| 533 | |
| 534 | /* --------------------------------------------- |
| 535 | * Disable the L2 prefetches. |
| 536 | * --------------------------------------------- |
| 537 | */ |
| 538 | bl cortex_a57_disable_l2_prefetch |
| 539 | |
| 540 | /* --------------------------------------------- |
| 541 | * Flush L1 caches. |
| 542 | * --------------------------------------------- |
| 543 | */ |
| 544 | mov r0, #DC_OP_CISW |
| 545 | bl dcsw_op_level1 |
| 546 | |
| 547 | /* --------------------------------------------- |
| 548 | * Disable the optional ACP. |
| 549 | * --------------------------------------------- |
| 550 | */ |
| 551 | bl plat_disable_acp |
| 552 | |
| 553 | /* --------------------------------------------- |
| 554 | * Flush L2 caches. |
| 555 | * --------------------------------------------- |
| 556 | */ |
| 557 | mov r0, #DC_OP_CISW |
| 558 | bl dcsw_op_level2 |
| 559 | |
| 560 | /* --------------------------------------------- |
| 561 | * Come out of intra cluster coherency |
| 562 | * --------------------------------------------- |
| 563 | */ |
| 564 | bl cortex_a57_disable_smp |
| 565 | |
| 566 | /* --------------------------------------------- |
| 567 | * Force the debug interfaces to be quiescent |
| 568 | * --------------------------------------------- |
| 569 | */ |
| 570 | pop {r12, lr} |
| 571 | b cortex_a57_disable_ext_debug |
| 572 | endfunc cortex_a57_cluster_pwr_dwn |
| 573 | |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 574 | #if REPORT_ERRATA |
| 575 | /* |
| 576 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 577 | */ |
| 578 | func cortex_a57_errata_report |
| 579 | push {r12, lr} |
| 580 | |
| 581 | bl cpu_get_rev_var |
| 582 | mov r4, r0 |
| 583 | |
| 584 | /* |
| 585 | * Report all errata. The revision-variant information is passed to |
| 586 | * checking functions of each errata. |
| 587 | */ |
| 588 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
| 589 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
| 590 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 591 | report_errata ERRATA_A57_814670, cortex_a57, 814670 |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 592 | report_errata ERRATA_A57_817169, cortex_a57, 817169 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 593 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 594 | disable_ldnp_overread |
| 595 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 596 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 597 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 598 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 599 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 600 | report_errata ERRATA_A57_859972, cortex_a57, 859972 |
Dimitris Papastamos | 8ca0af2 | 2018-01-03 10:48:59 +0000 | [diff] [blame] | 601 | report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 602 | report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 |
Dimitris Papastamos | 2b40ca6 | 2017-06-05 14:55:41 +0100 | [diff] [blame] | 603 | |
| 604 | pop {r12, lr} |
| 605 | bx lr |
| 606 | endfunc cortex_a57_errata_report |
| 607 | #endif |
| 608 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 609 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 610 | cortex_a57_reset_func, \ |
| 611 | cortex_a57_core_pwr_dwn, \ |
| 612 | cortex_a57_cluster_pwr_dwn |