Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 1 | /* |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 7 | #include <common/debug.h> |
| 8 | #include <drivers/arm/gic600_multichip.h> |
| 9 | #include <plat/arm/common/plat_arm.h> |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 10 | #include <plat/common/platform.h> |
Nishant Sharma | b57fa11 | 2022-07-13 10:19:58 +0100 | [diff] [blame] | 11 | #include <services/el3_spmc_ffa_memory.h> |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 12 | |
| 13 | #include <nrd_plat.h> |
| 14 | #include <nrd_soc_platform_def_v2.h> |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 15 | #include <rdn2_ras.h> |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 16 | |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 17 | #if defined(IMAGE_BL31) |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 18 | #if (NRD_PLATFORM_VARIANT == 2) |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 19 | static const mmap_region_t rdn2mc_dynamic_mmap[] = { |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 20 | #if NRD_CHIP_COUNT > 1 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 21 | ARM_MAP_SHARED_RAM_REMOTE_CHIP(1), |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 22 | NRD_MAP_DEVICE_REMOTE_CHIP(1), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 23 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 24 | #if NRD_CHIP_COUNT > 2 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 25 | ARM_MAP_SHARED_RAM_REMOTE_CHIP(2), |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 26 | NRD_MAP_DEVICE_REMOTE_CHIP(2), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 27 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 28 | #if NRD_CHIP_COUNT > 3 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 29 | ARM_MAP_SHARED_RAM_REMOTE_CHIP(3), |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 30 | NRD_MAP_DEVICE_REMOTE_CHIP(3), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 31 | #endif |
| 32 | }; |
| 33 | #endif |
| 34 | |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 35 | #if (NRD_PLATFORM_VARIANT == 2) |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 36 | static struct gic600_multichip_data rdn2mc_multichip_data __init = { |
| 37 | .rt_owner_base = PLAT_ARM_GICD_BASE, |
| 38 | .rt_owner = 0, |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 39 | .chip_count = NRD_CHIP_COUNT, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 40 | .chip_addrs = { |
| 41 | PLAT_ARM_GICD_BASE >> 16, |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 42 | #if NRD_CHIP_COUNT > 1 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 43 | (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 44 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 45 | #if NRD_CHIP_COUNT > 2 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 46 | (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 47 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 48 | #if NRD_CHIP_COUNT > 3 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 49 | (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 50 | #endif |
| 51 | }, |
| 52 | .spi_ids = { |
Varun Wadekar | 61286d2 | 2023-03-08 16:47:38 +0000 | [diff] [blame] | 53 | {PLAT_ARM_GICD_BASE, 32, 511}, |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 54 | #if NRD_CHIP_COUNT > 1 |
Varun Wadekar | 61286d2 | 2023-03-08 16:47:38 +0000 | [diff] [blame] | 55 | {PLAT_ARM_GICD_BASE, 512, 991}, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 56 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 57 | #if NRD_CHIP_COUNT > 2 |
Varun Wadekar | 61286d2 | 2023-03-08 16:47:38 +0000 | [diff] [blame] | 58 | {PLAT_ARM_GICD_BASE, 4096, 4575}, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 59 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 60 | #if NRD_CHIP_COUNT > 3 |
Varun Wadekar | 61286d2 | 2023-03-08 16:47:38 +0000 | [diff] [blame] | 61 | {PLAT_ARM_GICD_BASE, 4576, 5055}, |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 62 | #endif |
| 63 | } |
| 64 | }; |
| 65 | #endif |
| 66 | |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 67 | #if (NRD_PLATFORM_VARIANT == 2) |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 68 | static uintptr_t rdn2mc_multichip_gicr_frames[] = { |
| 69 | /* Chip 0's GICR Base */ |
| 70 | PLAT_ARM_GICR_BASE, |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 71 | #if NRD_CHIP_COUNT > 1 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 72 | /* Chip 1's GICR BASE */ |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 73 | PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 74 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 75 | #if NRD_CHIP_COUNT > 2 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 76 | /* Chip 2's GICR BASE */ |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 77 | PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 78 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 79 | #if NRD_CHIP_COUNT > 3 |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 80 | /* Chip 3's GICR BASE */ |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame^] | 81 | PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3), |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 82 | #endif |
| 83 | UL(0) /* Zero Termination */ |
| 84 | }; |
| 85 | #endif |
| 86 | #endif /* IMAGE_BL31 */ |
| 87 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 88 | unsigned int plat_arm_nrd_get_platform_id(void) |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 89 | { |
| 90 | return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) |
| 91 | & SID_SYSTEM_ID_PART_NUM_MASK; |
| 92 | } |
| 93 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 94 | unsigned int plat_arm_nrd_get_config_id(void) |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 95 | { |
| 96 | return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); |
| 97 | } |
| 98 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 99 | unsigned int plat_arm_nrd_get_multi_chip_mode(void) |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 100 | { |
| 101 | return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & |
| 102 | SID_MULTI_CHIP_MODE_MASK) >> |
| 103 | SID_MULTI_CHIP_MODE_SHIFT; |
| 104 | } |
| 105 | |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 106 | #if defined(IMAGE_BL31) |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 107 | void bl31_platform_setup(void) |
| 108 | { |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 109 | #if (NRD_PLATFORM_VARIANT == 2) |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 110 | int ret; |
| 111 | unsigned int i; |
| 112 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 113 | if (plat_arm_nrd_get_multi_chip_mode() == 0) { |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 114 | ERROR("Chip Count is %u but multi-chip mode is not enabled\n", |
| 115 | NRD_CHIP_COUNT); |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 116 | panic(); |
| 117 | } else { |
| 118 | INFO("Enabling multi-chip support for RD-N2 variant\n"); |
| 119 | |
| 120 | for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) { |
| 121 | ret = mmap_add_dynamic_region( |
| 122 | rdn2mc_dynamic_mmap[i].base_pa, |
| 123 | rdn2mc_dynamic_mmap[i].base_va, |
| 124 | rdn2mc_dynamic_mmap[i].size, |
| 125 | rdn2mc_dynamic_mmap[i].attr); |
| 126 | if (ret != 0) { |
| 127 | ERROR("Failed to add dynamic mmap entry for" |
| 128 | " i: %d " "(ret=%d)\n", i, ret); |
| 129 | panic(); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | plat_arm_override_gicr_frames( |
| 134 | rdn2mc_multichip_gicr_frames); |
| 135 | gic600_multichip_init(&rdn2mc_multichip_data); |
| 136 | } |
| 137 | #endif |
| 138 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 139 | nrd_bl31_common_platform_setup(); |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 140 | |
Manish Pandey | f90a73c | 2023-10-10 15:42:19 +0100 | [diff] [blame] | 141 | #if ENABLE_FEAT_RAS && FFH_SUPPORT |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 142 | nrd_ras_platform_setup(&ras_config); |
Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 143 | #endif |
Aditya Angadi | d61740b | 2020-11-19 18:05:33 +0530 | [diff] [blame] | 144 | } |
Aditya Angadi | ccae8a1 | 2021-08-09 09:38:58 +0530 | [diff] [blame] | 145 | #endif /* IMAGE_BL31 */ |
Nishant Sharma | 6733a5f | 2022-03-26 00:34:05 +0000 | [diff] [blame] | 146 | |
| 147 | #if SPMC_AT_EL3 |
| 148 | |
| 149 | #define DATASTORE_SIZE 1024 |
| 150 | |
| 151 | __section("arm_el3_tzc_dram") uint8_t plat_spmc_shmem_datastore[DATASTORE_SIZE]; |
| 152 | |
| 153 | int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) |
| 154 | { |
| 155 | *datastore = plat_spmc_shmem_datastore; |
| 156 | *size = DATASTORE_SIZE; |
| 157 | return 0; |
| 158 | } |
Nishant Sharma | b57fa11 | 2022-07-13 10:19:58 +0100 | [diff] [blame] | 159 | |
| 160 | /* |
| 161 | * Add dummy implementations of memory management related platform hooks. |
| 162 | * Memory share/lend operation are not required on RdN2 platform. |
| 163 | */ |
| 164 | int plat_spmc_shmem_begin(struct ffa_mtd *desc) |
| 165 | { |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) |
| 170 | { |
| 171 | return 0; |
| 172 | } |
Nishant Sharma | 44f285e | 2023-06-28 11:46:00 +0100 | [diff] [blame] | 173 | |
| 174 | int plat_spmd_handle_group0_interrupt(uint32_t intid) |
| 175 | { |
| 176 | /* |
| 177 | * As of now, there are no sources of Group0 secure interrupt enabled |
| 178 | * for RDN2. |
| 179 | */ |
| 180 | (void)intid; |
| 181 | return -1; |
| 182 | } |
Nishant Sharma | 6733a5f | 2022-03-26 00:34:05 +0000 | [diff] [blame] | 183 | #endif |