Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | include lib/libfdt/libfdt.mk |
| 8 | include lib/xlat_tables_v2/xlat_tables.mk |
| 9 | |
| 10 | PLAT_INCLUDES := -Iplat/rpi/common/include \ |
| 11 | -Iplat/rpi/rpi4/include |
| 12 | |
| 13 | PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ |
| 14 | plat/rpi/common/rpi3_common.c \ |
| 15 | ${XLAT_TABLES_LIB_SRCS} |
| 16 | |
| 17 | BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ |
| 18 | plat/rpi/rpi4/aarch64/plat_helpers.S \ |
Andre Przywara | 2d8e99a | 2019-07-10 18:09:18 +0100 | [diff] [blame^] | 19 | plat/rpi/rpi4/aarch64/armstub8_header.S \ |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 20 | drivers/arm/gic/common/gic_common.c \ |
| 21 | drivers/arm/gic/v2/gicv2_helpers.c \ |
| 22 | drivers/arm/gic/v2/gicv2_main.c \ |
| 23 | plat/common/plat_gicv2.c \ |
| 24 | plat/rpi/rpi4/rpi4_bl31_setup.c \ |
| 25 | plat/rpi/common/rpi3_pm.c \ |
| 26 | plat/common/plat_psci_common.c \ |
| 27 | plat/rpi/common/rpi3_topology.c \ |
| 28 | ${LIBFDT_SRCS} |
| 29 | |
| 30 | # For now we only support BL31, using the kernel loaded by the GPU firmware. |
| 31 | RESET_TO_BL31 := 1 |
| 32 | |
| 33 | # All CPUs enter armstub8.bin. |
| 34 | COLD_BOOT_SINGLE_CPU := 0 |
| 35 | |
| 36 | # Tune compiler for Cortex-A72 |
| 37 | ifeq ($(notdir $(CC)),armclang) |
| 38 | TF_CFLAGS_aarch64 += -mcpu=cortex-a72 |
| 39 | else ifneq ($(findstring clang,$(notdir $(CC))),) |
| 40 | TF_CFLAGS_aarch64 += -mcpu=cortex-a72 |
| 41 | else |
| 42 | TF_CFLAGS_aarch64 += -mtune=cortex-a72 |
| 43 | endif |
| 44 | |
Andre Przywara | 2d8e99a | 2019-07-10 18:09:18 +0100 | [diff] [blame^] | 45 | # Add support for platform supplied linker script for BL31 build |
| 46 | $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 47 | |
| 48 | # Enable all errata workarounds for Cortex-A72 |
| 49 | ERRATA_A72_859971 := 1 |
| 50 | |
| 51 | WORKAROUND_CVE_2017_5715 := 1 |
| 52 | |
| 53 | # Add new default target when compiling this platform |
| 54 | all: bl31 |
| 55 | |
| 56 | # Build config flags |
| 57 | # ------------------ |
| 58 | |
| 59 | # Disable stack protector by default |
| 60 | ENABLE_STACK_PROTECTOR := 0 |
| 61 | |
| 62 | # Have different sections for code and rodata |
| 63 | SEPARATE_CODE_AND_RODATA := 1 |
| 64 | |
| 65 | # Use Coherent memory |
| 66 | USE_COHERENT_MEM := 1 |
| 67 | |
| 68 | # Platform build flags |
| 69 | # -------------------- |
| 70 | |
| 71 | # Assume that BL33 isn't the Linux kernel by default |
| 72 | RPI3_DIRECT_LINUX_BOOT := 0 |
| 73 | |
| 74 | # BL33 images are in AArch64 by default |
| 75 | RPI3_BL33_IN_AARCH32 := 0 |
| 76 | |
| 77 | # UART to use at runtime. -1 means the runtime UART is disabled. |
| 78 | # Any other value means the default UART will be used. |
| 79 | RPI3_RUNTIME_UART := 0 |
| 80 | |
| 81 | # Use normal memory mapping for ROM, FIP, SRAM and DRAM |
| 82 | RPI3_USE_UEFI_MAP := 0 |
| 83 | |
| 84 | # Process platform flags |
| 85 | # ---------------------- |
| 86 | |
| 87 | $(eval $(call add_define,RPI3_BL33_IN_AARCH32)) |
| 88 | $(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) |
| 89 | ifdef RPI3_PRELOADED_DTB_BASE |
| 90 | $(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) |
| 91 | endif |
| 92 | $(eval $(call add_define,RPI3_RUNTIME_UART)) |
| 93 | $(eval $(call add_define,RPI3_USE_UEFI_MAP)) |
| 94 | |
| 95 | # Verify build config |
| 96 | # ------------------- |
| 97 | # |
| 98 | ifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) |
| 99 | ifndef RPI3_PRELOADED_DTB_BASE |
| 100 | $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) |
| 101 | endif |
| 102 | endif |
| 103 | |
| 104 | ifeq (${ARCH},aarch32) |
| 105 | $(error Error: AArch32 not supported on rpi4) |
| 106 | endif |
| 107 | |
| 108 | ifneq ($(ENABLE_STACK_PROTECTOR), 0) |
| 109 | PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ |
| 110 | plat/rpi/common/rpi3_stack_protector.c |
| 111 | endif |