Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. |
| 4 | * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | #include <common/interrupt_props.h> |
| 11 | #include <drivers/arm/gicv3.h> |
| 12 | #include <lib/utils.h> |
| 13 | #include <plat/common/platform.h> |
| 14 | |
| 15 | #include <plat_private.h> |
| 16 | #include <platform_def.h> |
| 17 | |
| 18 | /****************************************************************************** |
| 19 | * The following functions are defined as weak to allow a platform to override |
| 20 | * the way the GICv3 driver is initialised and used. |
| 21 | *****************************************************************************/ |
| 22 | #pragma weak plat_versal_net_gic_driver_init |
| 23 | #pragma weak plat_versal_net_gic_init |
| 24 | #pragma weak plat_versal_net_gic_cpuif_enable |
| 25 | #pragma weak plat_versal_net_gic_pcpu_init |
| 26 | |
| 27 | /* The GICv3 driver only needs to be initialized in EL3 */ |
| 28 | static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; |
| 29 | |
| 30 | static const uintptr_t gicr_base_addrs[2] = { |
| 31 | PLAT_VERSAL_NET_GICR_BASE, /* GICR Base address of the primary CPU */ |
| 32 | 0U /* Zero Termination */ |
| 33 | }; |
| 34 | |
| 35 | /* List of zero terminated GICR frame addresses which CPUs will probe */ |
| 36 | static const uintptr_t *gicr_frames; |
| 37 | |
| 38 | static const interrupt_prop_t versal_net_interrupt_props[] = { |
| 39 | PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S), |
| 40 | PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0) |
| 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register |
| 45 | * to core position. |
| 46 | * |
| 47 | * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity |
| 48 | * values read from GICR_TYPER don't have an MT field. To reuse the same |
| 49 | * translation used for CPUs, we insert MT bit read from the PE's MPIDR into |
| 50 | * that read from GICR_TYPER. |
| 51 | * |
| 52 | * Assumptions: |
| 53 | * |
| 54 | * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; |
| 55 | * - No CPUs implemented in the system use affinity level 3. |
| 56 | */ |
| 57 | static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr) |
| 58 | { |
| 59 | mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); |
| 60 | return plat_core_pos_by_mpidr(mpidr); |
| 61 | } |
| 62 | |
| 63 | static const gicv3_driver_data_t versal_net_gic_data __unused = { |
| 64 | .gicd_base = PLAT_VERSAL_NET_GICD_BASE, |
| 65 | .gicr_base = 0U, |
| 66 | .interrupt_props = versal_net_interrupt_props, |
| 67 | .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props), |
| 68 | .rdistif_num = PLATFORM_CORE_COUNT, |
| 69 | .rdistif_base_addrs = rdistif_base_addrs, |
| 70 | .mpidr_to_core_pos = versal_net_gicv3_mpidr_hash |
| 71 | }; |
| 72 | |
| 73 | void __init plat_versal_net_gic_driver_init(void) |
| 74 | { |
| 75 | /* |
| 76 | * The GICv3 driver is initialized in EL3 and does not need |
| 77 | * to be initialized again in SEL1. This is because the S-EL1 |
| 78 | * can use GIC system registers to manage interrupts and does |
| 79 | * not need GIC interface base addresses to be configured. |
| 80 | */ |
| 81 | #if IMAGE_BL31 |
| 82 | gicv3_driver_init(&versal_net_gic_data); |
| 83 | gicr_frames = gicr_base_addrs; |
| 84 | |
| 85 | if (gicv3_rdistif_probe(gicr_frames[0]) == -1) { |
| 86 | ERROR("No GICR base frame found for Primary CPU\n"); |
| 87 | panic(); |
| 88 | } |
| 89 | #endif |
| 90 | } |
| 91 | |
| 92 | /****************************************************************************** |
| 93 | * Versal NET common helper to initialize the GIC. Only invoked by BL31 |
| 94 | *****************************************************************************/ |
| 95 | void __init plat_versal_net_gic_init(void) |
| 96 | { |
| 97 | gicv3_distif_init(); |
| 98 | gicv3_rdistif_init(plat_my_core_pos()); |
| 99 | gicv3_cpuif_enable(plat_my_core_pos()); |
| 100 | } |
| 101 | |
| 102 | /****************************************************************************** |
| 103 | * Versal NET common helper to enable the GIC CPU interface |
| 104 | *****************************************************************************/ |
| 105 | void plat_versal_net_gic_cpuif_enable(void) |
| 106 | { |
| 107 | gicv3_cpuif_enable(plat_my_core_pos()); |
| 108 | } |
| 109 | |
| 110 | /****************************************************************************** |
| 111 | * Versal NET common helper to initialize the per-cpu redistributor interface in |
| 112 | * GICv3 |
| 113 | *****************************************************************************/ |
| 114 | void plat_versal_net_gic_pcpu_init(void) |
| 115 | { |
| 116 | int32_t result; |
| 117 | const uintptr_t *plat_gicr_frames = gicr_frames; |
| 118 | |
| 119 | do { |
| 120 | result = gicv3_rdistif_probe(*plat_gicr_frames); |
| 121 | |
| 122 | /* If the probe is successful, no need to proceed further */ |
| 123 | if (result == 0) { |
| 124 | break; |
| 125 | } |
| 126 | |
| 127 | plat_gicr_frames++; |
| 128 | } while (*plat_gicr_frames != 0U); |
| 129 | |
| 130 | if (result == -1) { |
| 131 | ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); |
| 132 | panic(); |
| 133 | } |
| 134 | |
| 135 | gicv3_rdistif_init(plat_my_core_pos()); |
| 136 | } |