blob: e0e479d21ce9e97dd56ec4efcb0de57087c49370 [file] [log] [blame]
Gary Morrison3d7f6542021-01-27 13:08:47 -06001/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef XLAT_MPU_PRIVATE_H
8#define XLAT_MPU_PRIVATE_H
9
10#include <stdbool.h>
11
12#include <lib/xlat_tables/xlat_tables_defs.h>
13#include <lib/xlat_tables/xlat_tables_v2.h>
14
15#include <platform_def.h>
16
17#if PLAT_XLAT_TABLES_DYNAMIC
18/*
19 * Private shifts and masks to access fields of an mmap attribute
20 */
21/* Dynamic or static */
22#define MT_DYN_SHIFT U(31)
23
24/*
25 * Memory mapping private attributes
26 *
27 * Private attributes not exposed in the public header.
28 */
29
30#endif /* PLAT_XLAT_TABLES_DYNAMIC */
31
32/* Calculate region-attributes byte for PRBAR part of MPU-region descriptor: */
33uint64_t prbar_attr_value(uint32_t attr);
34/* Calculate region-attributes byte for PRLAR part of MPU-region descriptor: */
35uint64_t prlar_attr_value(uint32_t attr);
36/* Calculates the attr value for a given PRBAR and PRLAR entry value: */
37uint32_t region_attr(uint64_t prbar_attr, uint64_t prlar_attr);
38
39#define PRBAR_PRLAR_ADDR_MASK UL(0xffffffffffc0)
40 /* mask for PRBAR & PRLAR MPU-region field */
41/* MPU region attribute bit fields: */
42#define PRBAR_SH_SHIFT UL(4)
43#define PRBAR_SH_MASK UL(0x3)
44#define PRBAR_AP_SHIFT UL(2)
45#define PRBAR_AP_MASK UL(0x3)
46#define PRBAR_XN_SHIFT UL(1)
47#define PRBAR_XN_MASK UL(0x3)
48#define PRLAR_NS_SHIFT UL(4)
49#define PRLAR_NS_MASK UL(0x3)
50#define PRBAR_ATTR_SHIFT UL(0)
51#define PRBAR_ATTR_MASK UL(0x3f)
52#define PRLAR_ATTR_SHIFT UL(1)
53#define PRLAR_ATTR_MASK UL(0x7)
54#define PRLAR_EN_SHIFT UL(0)
55#define PRLAR_EN_MASK UL(0x1)
56/* Aspects of the source attributes not defined elsewhere: */
57#define MT_PERM_MASK UL(0x1)
58#define MT_SEC_MASK UL(0x1)
59#define MT_EXECUTE_MASK UL(0x3)
60#define MT_TYPE_SHIFT UL(0)
61
62extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
63
64/*
65 * Return the execute-never mask that will prevent instruction fetch at the
66 * given translation regime.
67 */
68uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime);
69
70/* Print VA, PA, size and attributes of all regions in the mmap array. */
71void xlat_mmap_print(const mmap_region_t *mmap);
72
73/*
74 * Print the current state of the translation tables by reading them from
75 * memory.
76 */
77void xlat_tables_print(xlat_ctx_t *ctx);
78
79/*
80 * Returns a block/page table descriptor for the given level and attributes.
81 */
82uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
83 unsigned long long addr_pa, unsigned int level);
84
85/*
86 * Architecture-specific initialization code.
87 */
88
89/* Returns the current Exception Level. The returned EL must be 1 or higher. */
90unsigned int xlat_arch_current_el(void);
91
92/*
93 * Returns true if the MMU of the translation regime managed by the given
94 * xlat_ctx_t is enabled, false otherwise.
95 */
96bool is_mpu_enabled_ctx(const xlat_ctx_t *ctx);
97
98/*
99 * Returns minimum virtual address space size supported by the architecture
100 */
101uintptr_t xlat_get_min_virt_addr_space_size(void);
102
103#endif /* XLAT_MPU_PRIVATE_H */