blob: 4cf3bcfb3c99742191b673d06f37a12263d2fd04 [file] [log] [blame]
developera21d47e2019-05-02 19:29:25 +08001/*
2 * Copyright (c) 2019, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MTSPMC_H
8#define MTSPMC_H
9
10/*
11 * CONFIG_SPMC_MODE: Select CPU power control mode.
12 *
13 * 0: Legacy
14 * Control power flow from SW through SPM register (MP*_PWR_CON).
15 * 1: HW
16 * Control power flow from SPMC. Most control flow and timing are handled
17 * by SPMC.
18 */
19#define SPMC_MODE 1
20
21int spmc_init(void);
22
23void spm_poweron_cpu(int cluster, int cpu);
24void spm_poweroff_cpu(int cluster, int cpu);
25
26void spm_poweroff_cluster(int cluster);
27void spm_poweron_cluster(int cluster);
28
29int spm_get_cpu_powerstate(int cluster, int cpu);
30int spm_get_cluster_powerstate(int cluster);
31int spm_get_powerstate(uint32_t mask);
32
33void spm_enable_cpu_auto_off(int cluster, int cpu);
34void spm_disable_cpu_auto_off(int cluster, int cpu);
35void spm_set_cpu_power_off(int cluster, int cpu);
36void spm_enable_cluster_auto_off(int cluster);
37
38void mcucfg_init_archstate(int cluster, int cpu, int arm64);
39void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
40uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
41
42#endif /* MTSPMC_H */